When the PCI Special Interest Group (PCI-SIG) first announced PCIe 4.0 a few years back, the group made it clear that they were not just going to make up for lost time after PCIe 3.0, but that they were going to accelerate their development schedule to beat their old cadence. Since then the group has launched the final versions of the 4.0 and 5.0 specifications, and now with 5.0 only weeks old, the group is announcing today that they are already hard at work on the next version of the PCIe specification, PCIe 6.0. True to PCIe development iteration, the forthcoming standard will once again double the bandwidth of a PCIe slot – a x16 slot will now be able to hit a staggering 128GB/sec – with the group expecting to finalize the standard in 2021.

As with the PCIe iterations before it, the impetus for PCIe 6.0 is simple: hardware vendors are always in need of more bandwidth, and the PCI-SIG is looking to stay ahead of the curve by providing timely increases in bandwidth. Furthermore in the last few years their efforts have taken on an increased level of importance as well, as other major interconnect standards are building off of PCIe. CCIX, Intel’s CXL, and other interfaces have all extended PCIe, and will in turn benefit from PCIe improvements. So PCIe speed boosts serve as the core of building ever-faster (and more interconnected) systems.

PCIe 6.0, in turn, is easily the most important/most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. To be sure, PCIe 6.0 remains backwards compatible with the 5 versions that have preceded it, and PCIe slots aren’t going anywhere. But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn’t necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).

At a very high level, what PAM4 does versus NRZ is to take a page from the MLC NAND playbook, and double the number of electrical states a single cell (or in this case, transmission) will hold. Rather than traditional 0/1 high/low signaling, PAM4 uses 4 signal levels, so that a signal can encode for four possible two-bit patterns: 00/01/10/11. This allows PAM4 to carry twice as much data as NRZ without having to double the transmission bandwidth, which for PCIe 6.0 would have resulted in a frequency around 30GHz(!).

NRZ vs. PAM4 (Base Diagram Courtesy Intel)

PAM4 itself is not a new technology, but up until now it’s been the domain of ultra-high-end networking standards like 200G Ethernet, where the amount of space available for more physical channels is even more limited. As a result, the industry already has a few years of experience working with the signaling standard, and with their own bandwidth needs continuing to grow, the PCI-SIG has decided to bring it inside the chassis by basing the next generation of PCIe upon it.

The tradeoff for using PAM4 is of course cost. Even with its greater bandwidth per Hz, PAM4 currently costs more to implement at pretty much every level, from the PHY to the physical layer. Which is why it hasn’t taken the world by storm, and why NRZ continues to be used elsewhere. The sheer mass deployment scale of PCIe will of course help a lot here – economies of scale still count for a lot – but it will be interesting to see where things stand in a few years once PCIe 6.0 is in the middle of ramping up.

Meanwhile, not unlike the MLC NAND in my earlier analogy, because of the additional signal states a PAM4 signal itself is more fragile than a NRZ signal. And this means that along with PAM4, for the first time in PCIe’s history the standard is also getting Forward Error Correction (FEC). Living up to its name, Forward Error Correction is a means of correcting signal errors in a link by supplying a constant stream of error correction data, and it’s already commonly used in situations where data integrity is critical and there’s no time for a retransmission (such as DisplayPort 1.4 w/DSC). While FEC hasn’t been necessary for PCIe until now, PAM4’s fragility is going to change that. The inclusion of FEC shouldn’t make a noticeable difference to end-users, but for the PCI-SIG it’s another design requirement to contend with. In particular, the group needs to make sure that their FEC implementation is low-latency while still being appropriately robust, as PCIe users won’t want a significant increase in PCIe’s latency.

The upshot of the switch to PAM4 then is that by increasing the amount of data transmitted without increasing the frequency, the signal loss requirements won’t go up. PCIe 6.0 will have the same 36dB loss as PCIe 5.0, meaning that while trace lengths aren’t officially defined by the standard, a PCIe 6.0 link should be able to reach just as far as a PCIe 5.0 link. Which, coming from PCIe 5.0, is no doubt a relief to vendors and engineers alike.

Even with these changes, however, as previously mentioned PCIe 6.0 is fully backwards compatible with earlier standards, and this will go for both hosts and peripherals. This means that to a certain extent, hardware designers are essentially going to be implementing PCIe twice: once for NRZ, and again for PAM4. This will be handled at the PHY level, and while it’s not a true doubling of logic (what is NRZ but PAM4 with half as many signal levels?), it does mean that backwards compatibility is a bit more work this time around. Though discussing the matter in today’s press conference, it doesn’t sound like the PCI-SIG is terribly concerned about the challenges there, as PHY designers have proven quite capable (e.g. Ethernet).

PCI Express Bandwidth
(Full Duplex)
Slot Width PCIe 1.0
PCIe 2.0
PCIe 3.0
PCIe 4.0
PCIe 5.0
PCIe 6.0
x1 0.25GB/sec 0.5GB/sec ~1GB/sec ~2GB/sec ~4GB/sec ~8GB/sec
x2 0.5GB/sec 1GB/sec ~2GB/sec ~4GB/sec ~8GB/sec ~16GB/sec
x4 1GB/sec 2GB/sec ~4GB/sec ~8GB/sec ~16GB/sec ~32GB/sec
x8 2GB/sec 4GB/sec ~8GB/sec ~16GB/sec ~32GB/sec ~64GB/sec
x16 4GB/sec 8GB/sec ~16GB/sec ~32GB/sec ~64GB/sec ~128GB/sec

Putting all of this in practical terms then, PCIe 6.0 will be able to reach anywhere between ~8GB/sec for a x1 slot up to ~128GB/sec for a x16 slot (e.g. accelerator/video card). For comparison’s sake, 8GB/sec is as much bandwidth as a PCIe 2.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.

Overall, the PCI-SIG has set a rather aggressive schedule for this standard: the group has already been working on it, and would like to finalize the standard in 2021, two years from now. This would mean that the PCI-SIG will have improved PCIe’s bandwidth by eight-fold in a five-year period, going from PCIe 3.0 and its 8 GT/sec rate in 2016 to 4.0 and 16 GT/sec in 2017, 5.0 and 32 GT/sec in 2019, and finally 6.0 and 64 GT/sec in 2021. Which would be roughly half the time it has taken to get a similar increase going from PCIe 1.0 to 4.0.

As for end users and general availability of PCIe 6.0 products, while the PCI-SIG officially defers to the hardware vendors here, the launch cycles of PCIe 4.0 and 5.0 have been very similar, so PCIe 6.0 will likely follow in those same footsteps. 4.0, which was finalized in 2017, is just now showing up in mass market hardware in 2019, and meanwhile Intel has already committed to PCIe 5.0-capable CPUs in 2021. So we may see PCIe 6.0 hardware as soon as 2023, assuming development stays on track and hardware vendors move just as quickly to implement it as they have on earlier standards. Though for client/consumer use, it bears pointing out that with the rapid development pace for PCIe – and the higher costs that PAM4 will incur – just because the PCI-SIG develops 6.0 it doesn't mean it will show up in client decides any time soon; economics and bandwidth needs will drive that decision.

Speaking of which, as part of today’s press conference the group also gave a quick update on PCIe compliance testing and hardware rollouts. PCIe 4.0 compliance testing will finally kick off in August of this year, which should further accelerate 4.0 adoption and hardware support. Meanwhile PCIe 5.0 compliance testing is still under development, and like 4.0, once 5.0 compliance testing becomes available it should open the flood gates to much faster adoption there as well.

Source: PCI-SIG

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  • FreckledTrout - Wednesday, June 19, 2019 - link

    Of course there are in the serve space. Lots of compelling reasons for IO, networking, and many GPU's for compute.
  • Kevin G - Wednesday, June 19, 2019 - link

    PCIe 5.0 will have its spot in embedded and mobile where the reduction in trace lengths are not as critical to them. The benefit here is that fewer lanes will be necessary to reach a given bandwidth which leads to smaller chip packages and fewer traces on boards. The bonus here is that PCIe 5.0 is the ceiling as mobile/embedded can throttle down the clocks to 4.0 or 3.0 speeds if/when the extra bandwidth is not necessary to conserve power. More power efficient to run external buses at higher clocks than to go wider with more lanes

    A basic example would be M.2 SSDs of today that are generally 4x PCIe 3.0 which is the same bandwidth as 1x PCIe 5.0. Another example would be that a dual 10 Gbit NIC can run at full bandwidth with a single PCIe 5.0 lane to the host chip. 25GBaseT is also supposed to emerge in this time period which could also leverage narrow PCIe 5.0 support.
  • p1esk - Wednesday, June 19, 2019 - link

    Good point about single lane use cases, however I'm not sure many manufactures will want to change their designs so often (most probably are just now starting to think about adopting 4.0).
  • mode_13h - Wednesday, June 19, 2019 - link

    Given the consensus that 6.0 will be more expensive and dissipate higher-power than 5.0, I don't foresee 5.0 being skipped.
  • Valantar - Wednesday, June 19, 2019 - link

    Perhaps a dumb question, but here goes nonetheless: could this be made somehow backwards-compatible to allow for >PCIe 3.0 speeds on PCIe 3.0-spec boards (with updated controllers, obviously)? Given how the increased signalling frequency seems to be the main driver for shortening trace lengths and requiring redrivers with 4.0 (and even further with 5.0 from what I understand), could PAM4 be implemented at a lower frequency for effectively doubled transfer rates compared to 3.0 without dramatically affecting trace complexity? I get that a PAM4 signal is inherently more vulnerable to interference, but as the article states, it also has FEC to combat that.

    In other words, could PCIe 6.0 compatibility bring with it a "piggyback" double-speed protocol that can stack on top of previous standards? Given that any 6.0 host and device should be able to step down to 5.0 (which seems to be roughly "6.0 without PAM4"), 4.0, 3.0 and so on, could they then implement a "3.0+PAM4" or "4.0+PAM4" mode? In my mind it sounds feasible - and like a very good idea - but I'm no engineer.
  • SaturnusDK - Wednesday, June 19, 2019 - link

    Unfortunately no. As you may have noticed PAM4 relies on the receiver and transmitter to be able to decipher multiple voltage levels as multiple bits rolled into one. Effectively that means that each lane requires a low precision ADC and a DAC to read the multiple voltage levels. PCIe 3.0, 4.0 and 5.0 will not have such a requirement so there's no way they could decipher a multi-bit signal.
    You could argue that they could just add it as a "0.5" standard, sort of making it PCIe 3.5. So it'd be 3.0 with PAM4. However, the big problem is that using a multi-bit signal incurs a higher cost, adds more latency, and requires more power than just doubling the speed, even with the needed repeaters.
    So it doesn't make sense to use multi-bit signalling before you've run out feasible ways to just increasing the signalling speed.
  • willis936 - Wednesday, June 19, 2019 - link

    I think most PAM4 receivers actually demux into a serial NRZ stream and run that like a standard SerDes.
  • SaturnusDK - Wednesday, June 19, 2019 - link

    That's basically what I described. The poster above asked the question why we couldn't introduce multi-bit signalling with previous generations of PCIe and I gave the technical and physical reason on how we're going to design and implement PAM4 on PCIe 6.0.
  • willis936 - Wednesday, June 19, 2019 - link

    But I’m disagreeing. I don’t think the receivers are implementing multi bit ADCs. They demux the LSB and MSB and use zero crossing slicers. It’s different than typical multi bit ADCs made with resistor ladders or decoders. It’s different encoding and has different signal integrity characteristics.
  • repoman27 - Wednesday, June 19, 2019 - link

    PAM 4 doesn't multiplex two serial data streams, the SERDES simply encodes 2 bits per symbol. So instead of reading the signal level as either high or low for each transfer (like NRZ), a PAM4 receiver reads it as high, half-high, half-low, or low.

    And there is absolutely no chance of previous generation PCIe PHYs being able to adopt PAM4.

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