Update 07/02: Albeit a couple of days later than expected, the PCI-SIG has announced this morning that the PCI Express draft 0.71 specification has been released for member review. Following a minimum 30 day review process, the group will be able to publish the draft 0.9 version of the specficiation, putting them on schedule to release the final version of the spec this year.

Originally Published 05/25
As part of their yearly developer conference, the PCI Special Interest Group (PCI-SIG) also held their annual press briefing today, offering an update on the state of the organization and its standards. The star of the show, of course, was PCI Express 6.0, the upcoming update to the bus standard that will once again double its data transfer rate. PCI-SIG has been working on PCIe 6.0 for a couple of years now, and in a brief update, confirmed that the group remains on track to release the final version of the specification by the end of this year.

The most recent draft version of the specification, 0.7, was released back in November. Since then, PCI-SIG has remained at work collecting feedback from its members, and is gearing up to release another draft update next month. That draft will incorporate the all of the new protocol and electrical updates that have been approved for the spec since 0.7.

In a bit of a departure from the usual workflow for the group, however, this upcoming draft will be 0.71, meaning that PCIe 6.0 will be remaining at draft 0.7x status for a little while longer. The substance of this decision being that the group is essentially going to hold for another round of review and testing before finally clearing the spec to move on to the next major draft. Overall, the group’s rules call for a 30-day review period for the 0.71 draft, after which the group will be able to release the final draft 0.9 specification.

Ultimately, all of this is to say that PCIe 6.0 remains on track for its previously-scheduled 2021 release. After draft 0.9 lands, there will be a further two-month review for any final issues (primarily legal), and, assuming the standard clears that check, PCI-SIG will be able to issue the final, 1.0 version of the PCIe 6.0 specification.

In the interim, the 0.9 specification is likely to be the most interesting from a technical perspective. Once the updated electrical and protocol specs are approved, the group will be able to give some clearer guidance on the signal integrity requirements for PCIe 6.0. All told we’re not expecting much different from 5.0 (in other words, only a slot or two on most consumer motherboards), but as each successive generation ratchets up the signaling rate, the signal integrity requirements have tightened.

Overall, the unabashedly nerdy standards group is excited about the 6.0 standard, comparing it in significance to the big jump from PCIe 2.0 to PCIe 3.0. Besides proving that they’re once again able to double the bandwidth of the ubiquitous bus, it will mean that they’ve been able to keep to their goal of a three-year cadence. Meanwhile, as the PCIe 6.0 specification reaches completion, we should finally begin seeing the first PCIe 5.0 devices show up in the enterprise market.

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  • back2future - Wednesday, July 7, 2021 - link

    A comment made on Anandtech, mentioning that errors, because of error handling are a bigger influence to data bandwidth (what was probably within networking hardware news on x00Gbit/s devices) one might expect, could ask for the following (ethernet <> PCIe, NVlink overhead, transmit order?)
    %) What are error handling routines within PCIe protocol (transaction, data link, physical layer), received on "error reporting register(s)", what's their average impact and are there common stats available (PCIe2.x - PCIe5.0), so devices can be considered being within specification limits?
    %%) Are there new protocol versions or more likely driver conf parameters for data transfer that would not require, up to some amount of data, being retransmitted "free of errors" (like on AI inference methods, were predictions are made on probability) for then maybe increased throughput (configured from data analysts, application type)
    one reference https://www.kernel.org/doc/Documentation/PCI/pciea... (articles explaining are detailed on web, there are userspace log tools for summarized stats to that already before PCIe5-PCIe6?)
  • Golgatha777 - Wednesday, July 21, 2021 - link

    Looking forward to add-in cards for USB4, TB4, 10(+)GbE and M.2 SSDs with 1x or 2x interfaces on the consumer side. Eight 1x lanes with this kind of bandwidth is exciting for consumers.
  • damianrobertjones - Wednesday, July 21, 2021 - link

    "I/O bandwidth doubles every 3 years" - To ensure that we can milk customers over and over again.

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