It’s no secret that Intel’s enterprise processor platform has been stretched in recent generations. Compared to the competition, Intel is chasing its multi-die strategy while relying on a manufacturing platform that hasn’t offered the best in the market. That being said, Intel is quoting more shipments of its latest Xeon products in December than AMD shipped in all of 2021, and the company is launching the next generation Sapphire Rapids Xeon Scalable platform later in 2022. Beyond Sapphire Rapids has been somewhat under the hood, with minor leaks here and there, but today Intel is lifting the lid on that roadmap.

State of Play Today

Currently in the market is Intel’s Ice Lake 3rd Generation Xeon Scalable platform, built on Intel’s 10nm process node with up to 40 Sunny Cove cores. The die is large, around 660 mm2, and in our benchmarks we saw a sizeable generational uplift in performance compared to the 2nd Generation Xeon offering. The response to Ice Lake Xeon has been mixed, given the competition in the market, but Intel has forged ahead by leveraging a more complete platform coupled with FPGAs, memory, storage, networking, and its unique accelerator offerings. Datacenter revenues, depending on the quarter you look at, are either up or down based on how customers are digesting their current processor inventories (as stated by CEO Pat Gelsinger).

That being said, Intel has put a large amount of effort into discussing its 4th Generation Xeon Scalable platform, Sapphire Rapids. For example, we already know that it will be using >1600 mm2 of silicon for the highest core count solutions, with four tiles connected with Intel’s embedded bridge technology. The chip will have eight 64-bit memory channels of DDR5, support for PCIe 5.0, as well as most of the CXL 1.1 specification. New matrix extensions also come into play, along with data streaming accelerators, quick assist technology, all built on the latest P-core designs currently present in the Alder Lake desktop platform, albeit optimized for datacenter use (which typically means AVX512 support and bigger caches). We already know that versions of Sapphire Rapids will be available with HBM memory, and the first customer for those chips will be the Aurora supercomputer at Argonne National Labs, coupled with the new Ponte Vecchio high-performance compute accelerator.

The launch of Sapphire Rapids is significantly later than originally envisioned several years ago, but we expect to see the hardware widely available during 2022, built on Intel 7 process node technology.

Next Generation Xeon Scalable

Looking beyond Sapphire Rapids, Intel is finally putting materials into the public to showcase what is coming up on the roadmap. After Sapphire Rapids, we will have a platform compatible Emerald Rapids Xeon Scalable product, also built on Intel 7, in 2023. Given the naming conventions, Emerald Rapids is likely to be the 5th Generation.

Emerald Rapids (EMR), as with some other platform updates, is expected to capture the low hanging fruit from the Sapphire Rapids design to improve performance, as well as updates from the manufacturing. With platform compatibility, it means Emerald will have the same support when it comes to PCIe lanes, CPU-to-CPU connectivity, DRAM, CXL, and other IO features. We’re likely to see updated accelerators too. Exactly what the silicon will look like however is still an unknown. As we’re still new in Intel’s tiled product portfolio, there’s a good chance it will be similar to Sapphire Rapids, but it could equally be something new, such as what Intel has planned for the generation after.

After Emerald Rapids is where Intel’s roadmap takes on a new highway. We’re going to see a diversification in Intel’s strategy on a number of levels.

Starting at the top is Granite Rapids (GNR), built entirely of Intel’s performance cores, on an Intel 3 process node for launch in 2024. Previously Granite Rapids had been on roadmaps as an Intel 4 node product, however, Intel has stated to us that the progression of the technology as well as the timeline of where it will come into play makes it better to put Granite on that Intel 3 node. Intel 3 is meant to be Intel’s second-generation EUV node after Intel 4, and we expect the design rules to be very similar between the two, so it’s not that much of a jump from one to the other we suspect.

Granite Rapids will be a tiled architecture, just as before, but it will also feature a bifurcated strategy in its tiles: it will have separate IO tiles and separate core tiles, rather than a unified design like Sapphire Rapids. Intel hasn’t disclosed how they will be connected, but the idea here is that the IO tile(s) can contain all the memory channels, PCIe lanes, and other functionality while the core tiles can be focused purely on performance. Yes, it sounds like what Intel’s competition is doing today, but ultimately it’s the right thing to do.

Granite Rapids will share a platform with Intel’s new product line, which starts with Sierra Forest (SRF) which is also on Intel 3. This new product line will be built from datacenter optimized E-cores, which we’re familiar with from Intel’s current Alder Lake consumer portfolio. The E-cores in Sierra Forest will be a future generation than the Gracemont E-cores we have today, but the idea here is to provide a product that focuses more on core density rather than outright core performance. This allows them to run at lower voltages and parallelize, assuming the memory bandwidth and interconnect can keep up.

Sierra Forest will be using the same IO die as Granite Rapids. The two will share a platform – we assume in this instance this means they will be socket compatible – so we expect to see the same DDR and PCIe configurations for both. If Intel’s numbering scheme continues, GNR and SRF will be Xeon Scalable 6th Generation products. Intel stated to us in our briefing that the product portfolio currently offered by Ice Lake Xeon products will be covered and extended by a mix of GNR and SRF Xeons based on customer requirements. Both GNR and SRF are expected to have full global availability when launched.

The E-core Sierra Forest focused on core density will end up being compared to AMD’s equivalent, which for Zen4c will be called Bergamo – AMD might have a Zen5 equivalent when SRF comes to market.

I asked Intel whether the move to GNR+SRF on one unified platform means the generation after will be a unique platform, or whether it will retain the two-generation retention that customers like. I was told that it would be ideal to maintain platform compatibility across the generations, although as these are planned out, it depends on timing and where new technologies need to be integrated. The earliest industry estimates (beyond CPU) for PCIe 6.0 are in the 2026 timeframe, and DDR6 is more like 2029, so unless there are more memory channels to add it’s likely we’re going to see parity between 6th and 7th Gen Xeon.

My other question to Intel was about Hybrid CPU designs – if Intel was now going to make P-core tiles and E-core tiles, what’s stopping a combined product with both? Intel stated that their customers prefer uni-core designs in this market as the needs from customer to customer differ. If one customer prefers an 80/20 split on P-cores to E-cores, there’s another customer that prefers a 20/80 split. Having a wide array of products for each different ratio doesn’t make sense, and customers already investigating this are finding out that the software works better with a homogeneous arrangement, instead split at the system level, rather than the socket level. So we’re not likely to see hybrid Xeons any time soon. (Ian: Which is a good thing.)

I did ask about the unified IO die - giving the same P-core only and E-core only Xeons the same number of memory channels and I/O lanes might not be optimal for either scenario. Intel didn’t really have a good answer here, aside from the fact that building them both into the same platform helped customers synergize non-returnable development costs across both CPUs, regardless of the one they used. I didn’t ask at the time, but we could see the door open to more Xeon-D-like scenarios with different IO configurations for smaller deployments, but we’re talking products that are 2-3+ years away at this point.

Xeon Scalable Generations
Date AnandTech Codename Abbr. Max
Cores
Node Socket
Q3 2017 1st Skylake SKL 28 14nm LGA 3647
Q2 2019 2nd Cascade Lake CXL 28 14nm LGA 3647
Q2 2020 3rd Cooper Lake CPL 28 14nm LGA 4189
Q2 2021 Ice Lake ICL 40 10nm LGA 4189
2022 4th Sapphire Rapids SPR * Intel 7 LGA 4677
2023 5th Emerald Rapids EMR ? Intel 7 **
2024 6th Granite Rapids GNR ? Intel 3 ?
Sierra Forest SRF ? Intel 3
>2024 7th Next-Gen P ? ? ? ?
Next-Gen E
* Estimate is 56 cores
** Estimate is LGA4677

For both Granite Rapids and Sierra Forest, Intel is already working with key ‘definition customers’ for microarchitecture and platform development, testing, and deployment. More details to come, especially as we move through Sapphire and Emerald Rapids during this year and next.

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  • Silver5urfer - Thursday, February 17, 2022 - link

    Ian: Which is a good thing.

    100% agreed with that Ian. DC do not like this hybrid nonsense, esp if we look at VMWare and their licensing systems plus how the VMs and Containers work with the Hypervisors on top of the reduced instruction set is a mess. Plus a scheduler must operate at such hyperscale it will be a gigantic waste of money.

    Intel had to do this on Mainstream because of their IPC target and SMT performance target vs AMD, who are very much ahead in SMT specifically. Also the whole LGA1700 CPUs are got and high density heat far more than RKL which was too hot. So they had to axe the P cores to make them Clock at 5GHz and get the maximum SMT performance too. Now they knew that E cores will get them that performance needed they segment them with Raptor Lake now, having more Cores on E side to get that SMT competitiveness vs upcoming monster Zen 4.

    As for Xeon they do not have to clock at such high frequencies plus the SMT performance is already there due to that Multisocket system and other bells and whistles.

    Finally on the AMD vs Intel side, looks like Intel will be more competitive with AMD when their E cores Xeon comes out, rough guess. Also this move is done by both AMD and Intel because they want to stop ARM Server processors which do not have SMT technology but high density in Cores.

    Good to know some roadmap. All I want to see is a real successor to X299. AMD pathetically axed the Threadrippers horribly, Gen 1 got 2 CPU refresh but 3rd was purposefully axed to get more cash on the sTRX socket. And now no Zen 3 based Threadripper nor a damn 3DV enhanced Threadripper (on top of how they didn't care for 3DV on AM4 because Zen 4 needs to be strong and more sales from new chipset / socket AM5).
    Reply
  • ballsystemlord - Thursday, February 17, 2022 - link

    I share your frustration at Threadripper's loss. Reply
  • Abort-Retry-Fail - Friday, February 18, 2022 - link


    Threadripper Pro is competing with itself. I know - I've been breaking one in for 9 months. There are no limits for the TR Pro in content creation for performance and efficiency in HEDT. Castle Peak sWRX8 is 'Zen2' - future variants will be 'slobber-knockers' to the competition.

    No offense, but Chipzillah continues to shoot itself in both feet. Everyone knows 'Intel 7' is 10nm +++ 'Enhanced SuperFin' regardless of marketing and 'branding'
    Reply
  • drothgery - Friday, February 18, 2022 - link

    Yes, but most people don't know TSMC N7 being routinely called "7nm" is branding too. Reply
  • nandnandnand - Friday, February 18, 2022 - link

    The only question is whether Intel 7 is comparable to TSMC N7, Intel 4 to TSMC N4, etc. Reply
  • kwohlt - Sunday, February 20, 2022 - link

    Most people don't know that "10nm +++" is also marketing and branding. They're just names. If Intel 7 is comparable to TSMC 7nm, than they're competitors and the rename makes sense. Pointing out that the original plan was to call it 10nm ESF is rather pointless and borderline misleads people into thinking the node is a generation behind, technologically (it's not) Reply
  • Spunjji - Tuesday, February 22, 2022 - link

    Indeed, it's not. After 6 years Intel finally massaged its 10nm process into something that's roughly as good as TSMC N7, so the rename makes sense as a marketing break from the absolute failboat that was the 10nm / 10nm(+) / 10nm+(+[SF]) / 10nm++(+[ESF]) nomenclature. Reply
  • mattj0707 - Tuesday, February 22, 2022 - link

    It IS in fact on par with TSMC's 7nm and in some areas, it is better than TSMC's 7nm node. In two areas specifically, Intel 7 outpeforms TSMC. That is transistor density (Intel 7 node is more denser than TSMC) and Intel 7 outperforms TSMC 7 in transistor leakage and drive current. That is exactly why Intel's Alder Lake chips are easily boosting to 5 GHz on mobile w/ little power consumption and their desktop chips are boosting to sustained clocks above 5 GHz. And Intel's new release of their KS skus can achieve clocks on multiple cores upt to 5.5 GHz sustained. TSMC N7 could never reach that sort of drive current and those clocks. It was only recently that AMD's Ryzen chips were able to briefly boost to 4.9 or 5 GHz. TSMC's N7 is a good node, especially for power efficiency, but it is just a fact that Intel 7 outperforms it. Reply
  • mode_13h - Wednesday, February 23, 2022 - link

    I assume most know this, but clock speed isn't just a function of the process node. It also has to do with circuit design. A chip designed with longer critical paths will have less ability to reach high clockspeeds, but the tradeoff is that it's probably be doing more real work per cycle.

    And this might reveal a downside of AMD's strategy of sharing chiplets between desktop and servers. Since servers place a greater premium on power-efficiency, that keeps downward pressure on clock speed and therefore greater incentive to utilize longer critical paths. Meanwhile, Intel tweaks their core designs and fabs completely separate dies for server CPUs vs. other markets.
    Reply
  • mattj0707 - Tuesday, February 22, 2022 - link

    Intel 7 is definitely comparable to TSMC N7. Node names don't have any correlation to the actual features, performance or efficiency of the transistors themselves. We know for a fact that Intel 7 outperforms TSMC N7 in a few areas like transistor density, leakage, and drive current. So regardless if its called Intel 7 or 10 nm++++, it's performance is on par with TSMC's N7 so who cares what it's called at the end of the day. The performance is what matters, not the marketing name. Reply

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