The Architecture

We'll start, logically, at the front end of a Bulldozer module. The fetch and decode logic in each module is shared by both integer cores. The role this logic plays is to fetch the next instruction in the thread being executed, decode the x86 instruction into AMD's own internal format, and pass the decoded instruction onto the scheduling hardware for execution.

AMD widened the K8 front end with Bulldozer. Each module is now able to fetch and decode up to four x86 instructions from a single thread in parallel. Each of the four decoders are equally capable. Remembering that each Bulldozer module appears as two cores, the front end can only pick 4 instructions to fetch and decode from a single thread at a time. A single Bulldozer module can switch between threads as often as every clock.

Decode hardware isn't very expensive on its own, but duplicating it four times across multiple cores quickly adds up. Although decode width has increased for a single core, multi-core Bulldozer configurations can actually be at a disadvantage compared to previous AMD architectures. Let's look at the table below to understand why:

Front End Comparison
  AMD Phenom II AMD FX Intel Core i7
Instruction Decode Width 3-wide 4-wide 4-wide
Single Core Peak Decode Rate 3 instructions 4 instructions 4 instructions
Dual Core Peak Decode Rate 6 instructions 4 instructions 8 instructions
Quad Core Peak Decode Rate 12 instructions 8 instructions 16 instructions
Six/Eight Core Peak Decode Rate 18 instructions (6C) 16 instructions 24 instructions (6C)

For a single instruction thread, Bulldozer offers more front end bandwidth than its predecessor. The front end is wider and just as capable so this makes sense. But note what happens when we scale up core count.

Since fetch and decode hardware is shared per module, and AMD counts each module as two cores, given an equivalent number of cores the old Phenom II actually offers a higher peak instruction fetch/decode rate than the FX. The theory is obviously that the situations where you're fetch/decode bound are infrequent enough to justify the sharing of hardware. AMD is correct for the most part. Many instructions can take multiple cycles to decode, and by switching between threads each cycle the pipelined front end hardware can be more efficiently utilized. It's only in unusually bursty situations where the front end can become a limit.

Compared to Intel's Core architecture however, AMD is at a disadvantage here. In the high-end offerings where Intel enables Hyper Threading, AMD has zero advantage as Intel can weave in instructions from two threads every clock. It's compared to the non-HT enabled Core CPUs that the advantage isn't so clear. Intel maintains a higher instantaneous decode bandwidth per clock, however overall decoder utilization could go down as a result of only being able to fill each fetch queue from a single thread.

After the decoders AMD enables certain operations to be fused together and treated as a single operation down the rest of the pipeline. This is similar to what Intel calls micro-ops fusion, a technology first introduced in its Banias CPU in 2003. Compare + branch, test + branch and some other operations can be fused together after decode in Bulldozer—effectively widening the execution back end of the CPU. This wasn't previously possible in Phenom II and obviously helps increase IPC.

A Decoupled Branch Predictor

AMD didn't disclose too much about the configuration of the branch predictor hardware in Bulldozer, but it is quick to point out one significant improvement: the branch predictor is now significantly decoupled from the processor's front end.

The role of the branch predictor is to intercept branch instructions and predict their target address, rather than allowing for tons of cycles to go by until the branch target is known for sure. Branches are predicted based on historical data. The more data you have, and the better your branch predictors are tuned to your workload, the more accurate your predictions can be. Accurate branch prediction is particularly important in architectures with deep pipelines as a mispredict causes more instructions to be flushed out of the pipe. Bulldozer introduces a significantly deeper pipeline than its predecessor (more on this later), and thus branch prediction improvements are necessary.

In both Phenom II and Bulldozer, branches are predicted in the front end of the pipe alongside the fetch hardware. In Phenom II however, any stall in the fetch pipeline (e.g. fetching an instruction that wasn't in cache) would stop the whole pipeline including future branch predictions. Bulldozer decouples the branch prediction hardware from the fetch pipeline by way of a prediction queue. If there's a stall in the fetch pipeline, Bulldozer's branch prediction hardware is allowed to run ahead and continue making future predictions until the prediction queue is full.

We'll get to the effectiveness of this approach shortly.

Scheduling and Execution Improvements

As with Sandy Bridge, AMD migrated to a physical register file architecture with Bulldozer. Data is now only stored in one location (the physical register file) and is tracked via pointers back to the PRF as operations make their way through the execution engine. This is a move to save power as copying data around a chip is hardly power efficient.

The buffers and queues that feed into the execution engines of the chip are all larger on Bulldozer than they were on Phenom II. Larger data structures allows for better instruction level parallelism when trying to execute operations out of order. In other words, the issue hardware in Bulldozer is beefier than its predecessor.

Unfortunately where AMD took one step forward in issue hardware, it does a bit of a shuffle when it comes to execution resources themselves. Let's start with the positive: Bulldozer's integer execution cores.

Integer Execution

Each Bulldozer module features two fully independent integer cores. Each core has its own integer scheduler, register file and 16KB L1 data cache. The integer schedulers are both larger than their counterparts in the Phenom II.

The biggest change here is each integer core now has two ports instead of three. A single integer core features two AGU/ALU ports, compared to three in the previous design. AMD claims the third ALU/AGU pair went mostly unused in Phenom II, and as a result it's been removed from Bulldozer.

With larger structures feeding into the integer cores, AMD should be able to have an easier time of making use of the integer units than in previous designs. AMD could, in theory, execute more integer operations per core in Phenom II however AMD claims the architecture was typically bound elsewhere.

The Shared FP Core

A single Bulldozer module has a single shared FP core for use by up to two threads. If there's only a single FP thread available, it is given full access to the FP execution hardware, otherwise the resources are shared between the two threads.

Compared to a quad-core Phenom II, AMD's eight-core (quad-module) FX sees no drop in floating point execution resources. AMD's architecture has always had independent scheduling for integer and floating point instructions, and we see the same number of execution ports between Phenom II cores and FX modules. Just as is the case with the integer cores, the shared FP core in a Bulldozer module has larger scheduling hardware in front of it than the FPU in Phenom II.

The problem is AMD had to increase the functionality of its FPU with the move to Bulldozer. The Phenom II architecture lacks SSE4 and AVX support, both of which were added in Bulldozer. Furthermore, AMD chose Bulldozer as the architecture to include support for fused multiply-add instructions (FMA). Enabling FMA support also increases the relative die area of the FPU. So while the throughput of Bulldozer's FPU hasn't increased over K8, its capabilities have. Unfortunately this means that peak FP throughput running x87/SSE2/3 workloads remains unchanged compared to the previous generation. Bulldozer will only be faster if newer SSE, AVX or FMA instructions are used, or if its clock speed is significantly higher than Phenom II.

Looking at our Cinebench 11.5 multithreaded workload we see the perfect example of this performance shuffle:

Cinebench 11.5—Multi-Threaded

Despite a 9% higher base clock speed (more if you include turbo core), a 3.6GHz 8-core Bulldozer is only able to outperform a 3.3GHz 6-core Phenom II by less than 2%. Heavily threaded floating point workloads may not see huge gains on Bulldozer compared to their 6-core predecessors.

There's another issue. Bulldozer, at least at launch, won't have to simply outperform its quad-core predecessor. It will need to do better than a six-core Phenom II. In this comparison unfortunately, the Phenom II has the definite throughput advantage. The Phenom II X6 can execute 50% more SSE2/3 and x87 FP instructions than a Bulldozer based FX.

Since the release of the Phenom II X6, AMD's major advantage has been in heavily threaded workloads—particularly floating point workloads thanks to the sheer number of resources available per chip. Bulldozer actually takes a step back in this regard and as a result, you will see some of those same workloads perform worse, if not the same as the outgoing Phenom II X6.

Compared to Sandy Bridge, Bulldozer only has two advantages in FP performance: FMA support and higher 128-bit AVX throughput. There's very little code available today that uses AMD's FMA instruction, while the 128-bit AVX advantage is tangible.

Cache Hierarchy and Memory Subsystem

Each integer core features its own dedicated L1 data cache. The shared FP core sends loads/stores through either of the integer cores, similar to how it works in Phenom II although there are two integer cores to deal with now instead of just one. Bulldozer enables fully out-of-order loads and stores, an improvement over Phenom II putting it on parity with current Intel architectures. The L1 instruction cache is shared by the entire bulldozer module, as is the L2 cache.

The instruction cache is a large 64KB 2-way set associative cache, similar in size to the Phenom II's L1 cache but obviously shared by more "cores". A four-core Phenom II would have 256KB of total L1 I-Cache, while a four core Bulldozer will have half of that. The L1 data caches are also significantly smaller than Bulldozer's predecessor. While Phenom II offered a 64KB L1 D-Cache per core, Bulldozer only offers 16KB per integer core.

The L2 cache is much larger than what we saw in multi-core Phenom II designs however. Each Bulldozer module has a private 2MB L2 cache.

There's a single 8MB L3 cache that's shared among all Bulldozer modules on a chip. In its first incarnation, AMD has no plans to offer a desktop part without an L3 cache. However AMD indicated that the L3 cache was only really useful in server workloads and we might expect future Bulldozer derivatives (ahem, Trinity?) to forgo the L3 cache entirely as a result.

Cache accesses require more clocks in Bulldozer, due to a combination of size and AMD's desire to make Bulldozer a very high clock speed part...

Introduction The Pursuit of Clock Speed
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  • GatorLord - Thursday, October 13, 2011 - link

    OMG! That is some seriously funny sh1t! I thought I'd blow a kidney or something...I'm trying to type this though the tears I was laughing so hard!
  • I800C0LLECT - Thursday, October 13, 2011 - link

    I think majority of these comments show just how fickle consumerism is in America. Anyways, tomorrow's vision vs. current real world performance is the rats nest.

    They obviously pushed this towards server markets. Maybe that's why there wasn't much fanfare with the marketing gurus?

    The performance obviously doesn't reach out to the niche market of computer gamers. Let's see how lucrative this becomes if AMD is able to crack the not so trendy server market. Those guys don't like to break old habits. Stability is kind of a big deal.

    I can also see how this design creates a plug and play product for many different markets. The downside to that is it's one design for all which has already proven inefficient for Gamers. But what about consumer electronics? They generally want cheap and simple. Performance be damned.

    Interesting hand AMD.
  • CharlieBBarkin - Thursday, October 13, 2011 - link

    I'd hate to break it to you, but even though Bulldozer was targeted towards the server market, it is a complete non-starter in that segment. Look at the power consumption of the Bulldozer. It's off the charts, and it has less raw performance than Intel chips. I can't imagine any system administrator dumb enough to install Bulldozer chips into any sort of compute or server farm. Why would a farm waste money powering and cooling Bulldozer chips when it would be so much cheaper and higher performance to just use Intel CPUs?
  • silverblue - Friday, October 14, 2011 - link

    Could just be the ASUS board causing the issues. At any rate, once you overclock past a certain point, power usage just accelerates madly, and you're not going to see these sorts of high frequencies on the server anyway so the point is rather moot. Additionally, with servers, they're a little more focused on power efficiency than with client machines. Magny Cours was a 12-core CPU and the 6176 had a TDP of 105W if I'm correct, so despite its 2.3GHz clock speed, that's not too bad considering.
  • luckylinux - Thursday, October 13, 2011 - link

    I also have waited for a long time to finally see if I could replace my phenom ii x4 and x6 with the new super bulldozer. Nevertheless I'm pretty disappointed by the raw performance of this new chip.
    I began using amd products about one year and a half ago, so I'm not really an amd fanboy ... however began to like them for their choice of not doing the intel shitty hobby of switching 3 sockets every 2 years.
    Took an athlon x2, x4, phenom ii x6 and two E-350 from them and very happy for what you get (a bang for your money).

    However ... looking at the athlons (and even more the phenoms) power consumption is rather disappointing compared to sandy bridge cpus which I recently bought (yeah, I did not want to leave a 24/7 machine on drawing 60 Watts at idle when SB idles at much less with their power gates tech).
    Bulldozer power gates are rather disappointing. Hoped for much higher frequency or lower power consumption at load due to the transistor shrink. And 2B transistors ????? Seeing as some compenents are shared across cores I think this is WAY too much !

    BUT one thing deserves to be said. In my case (but that's just me, eh) I wanted a multicore processor which supported both AES-NI and ECC memory. For ECC you can either take an ASUS AM3(+) motherboard (about 120$ the cheapests of am3+), either a 1366 or a 1155 C202/4/6, which costs about 260$ at least ! For AES-NI the only alternative seemed up til now to go with Xeon which cost quite a bit more. Furthermore Xeon cpus are not so easily to get your hands on.
    I think that no one gave credit for their efforts to implement AES-NI. If you want a home server that's a very appreciated bonus.
    Although I can understand why many of the users here are angry at the new chip because it doesn't perform very well in gaming, the choice of amd to disregard single threaded apps in itself is quite good. In a market where in a few years we'll see 40+ cores on a single desktop CPU (well, in server that'll be next year with Komodo !) what the heck can you obtain with a single core ? Idling 39 cores to speed up one core to 8GHz (assuming that's electrically possible). Silicon dictates the limits on the frequency you can use in your chip. AMD understood this long ago, when intel and their S775 tried to surpass the 3GHz wall with the Pentium IV. Since we're going in a multithread world, 40 x 4GHz (something like that at 22 or 10nm I think) will perform WAY better that 1 x 8GHz (provided that apps are well developed). Why INTEL does not understand this (S2011 provides only 6 cores !) ? However with 2B transistors a few more cores could've been added :D AMD has to work better at power consumption. Instead of clock per clock performance they focus on # of cores which is what the future is ! You will say that intel's performance per core is almost the double, but amd cores are twice so ... How long will intel continue to release quads when amd'll get to sixteen ? If you're an intel fanboy just say that amd BD is shit, but I think this kind of strategy is going to pay in the long term. In fact amd manages to put more cores in a single die, whereas intel is always 2 cores behind. That alone shows that AMD engineers aren't idiots !
  • luckylinux - Thursday, October 13, 2011 - link

    EDIT: Komodo will have 20cores (only :D)
  • I800C0LLECT - Thursday, October 13, 2011 - link

    More cores?

    I guess I was trying to infer that as fabrication processes we shrink to 22nm, etc. How much over head is reduced by plugging in a few more cores vs. new design and architecture?

    I'm wondering if AMD just set the foundation for something big?

    Seems like they bet on software making some leaps and bounds.
  • wolfman3k5 - Thursday, October 13, 2011 - link

    It's finally here! I have been waiting for one of these. It's another Hitler Video, this time it's about Bulldozer. Funny as hell...

    The video can be found here: http://www.youtube.com/watch?v=SArxcnpXStE
  • just4U - Thursday, October 13, 2011 - link

    Ok, in several reviews now I've heard about the lacklustre single threaded performance.. Just how bad is it? If you had to compare it to another cpu out there which intel and which amd cput would it compare to?
  • Desperad@ - Thursday, October 13, 2011 - link

    Promises of AMD
    http://blogs.amd.com/work/2010/08/23/%E2%80%9Dbull...
    http://blogs.amd.com/work/2010/08/30/bulldozer-20-...
    http://blogs.amd.com/work/2010/09/13/bulldozer-20-...
    http://sites.amd.com/us/promo/processors/Pages/ope...

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