The Architecture

We'll start, logically, at the front end of a Bulldozer module. The fetch and decode logic in each module is shared by both integer cores. The role this logic plays is to fetch the next instruction in the thread being executed, decode the x86 instruction into AMD's own internal format, and pass the decoded instruction onto the scheduling hardware for execution.

AMD widened the K8 front end with Bulldozer. Each module is now able to fetch and decode up to four x86 instructions from a single thread in parallel. Each of the four decoders are equally capable. Remembering that each Bulldozer module appears as two cores, the front end can only pick 4 instructions to fetch and decode from a single thread at a time. A single Bulldozer module can switch between threads as often as every clock.

Decode hardware isn't very expensive on its own, but duplicating it four times across multiple cores quickly adds up. Although decode width has increased for a single core, multi-core Bulldozer configurations can actually be at a disadvantage compared to previous AMD architectures. Let's look at the table below to understand why:

Front End Comparison
  AMD Phenom II AMD FX Intel Core i7
Instruction Decode Width 3-wide 4-wide 4-wide
Single Core Peak Decode Rate 3 instructions 4 instructions 4 instructions
Dual Core Peak Decode Rate 6 instructions 4 instructions 8 instructions
Quad Core Peak Decode Rate 12 instructions 8 instructions 16 instructions
Six/Eight Core Peak Decode Rate 18 instructions (6C) 16 instructions 24 instructions (6C)

For a single instruction thread, Bulldozer offers more front end bandwidth than its predecessor. The front end is wider and just as capable so this makes sense. But note what happens when we scale up core count.

Since fetch and decode hardware is shared per module, and AMD counts each module as two cores, given an equivalent number of cores the old Phenom II actually offers a higher peak instruction fetch/decode rate than the FX. The theory is obviously that the situations where you're fetch/decode bound are infrequent enough to justify the sharing of hardware. AMD is correct for the most part. Many instructions can take multiple cycles to decode, and by switching between threads each cycle the pipelined front end hardware can be more efficiently utilized. It's only in unusually bursty situations where the front end can become a limit.

Compared to Intel's Core architecture however, AMD is at a disadvantage here. In the high-end offerings where Intel enables Hyper Threading, AMD has zero advantage as Intel can weave in instructions from two threads every clock. It's compared to the non-HT enabled Core CPUs that the advantage isn't so clear. Intel maintains a higher instantaneous decode bandwidth per clock, however overall decoder utilization could go down as a result of only being able to fill each fetch queue from a single thread.

After the decoders AMD enables certain operations to be fused together and treated as a single operation down the rest of the pipeline. This is similar to what Intel calls micro-ops fusion, a technology first introduced in its Banias CPU in 2003. Compare + branch, test + branch and some other operations can be fused together after decode in Bulldozer—effectively widening the execution back end of the CPU. This wasn't previously possible in Phenom II and obviously helps increase IPC.

A Decoupled Branch Predictor

AMD didn't disclose too much about the configuration of the branch predictor hardware in Bulldozer, but it is quick to point out one significant improvement: the branch predictor is now significantly decoupled from the processor's front end.

The role of the branch predictor is to intercept branch instructions and predict their target address, rather than allowing for tons of cycles to go by until the branch target is known for sure. Branches are predicted based on historical data. The more data you have, and the better your branch predictors are tuned to your workload, the more accurate your predictions can be. Accurate branch prediction is particularly important in architectures with deep pipelines as a mispredict causes more instructions to be flushed out of the pipe. Bulldozer introduces a significantly deeper pipeline than its predecessor (more on this later), and thus branch prediction improvements are necessary.

In both Phenom II and Bulldozer, branches are predicted in the front end of the pipe alongside the fetch hardware. In Phenom II however, any stall in the fetch pipeline (e.g. fetching an instruction that wasn't in cache) would stop the whole pipeline including future branch predictions. Bulldozer decouples the branch prediction hardware from the fetch pipeline by way of a prediction queue. If there's a stall in the fetch pipeline, Bulldozer's branch prediction hardware is allowed to run ahead and continue making future predictions until the prediction queue is full.

We'll get to the effectiveness of this approach shortly.

Scheduling and Execution Improvements

As with Sandy Bridge, AMD migrated to a physical register file architecture with Bulldozer. Data is now only stored in one location (the physical register file) and is tracked via pointers back to the PRF as operations make their way through the execution engine. This is a move to save power as copying data around a chip is hardly power efficient.

The buffers and queues that feed into the execution engines of the chip are all larger on Bulldozer than they were on Phenom II. Larger data structures allows for better instruction level parallelism when trying to execute operations out of order. In other words, the issue hardware in Bulldozer is beefier than its predecessor.

Unfortunately where AMD took one step forward in issue hardware, it does a bit of a shuffle when it comes to execution resources themselves. Let's start with the positive: Bulldozer's integer execution cores.

Integer Execution

Each Bulldozer module features two fully independent integer cores. Each core has its own integer scheduler, register file and 16KB L1 data cache. The integer schedulers are both larger than their counterparts in the Phenom II.

The biggest change here is each integer core now has two ports instead of three. A single integer core features two AGU/ALU ports, compared to three in the previous design. AMD claims the third ALU/AGU pair went mostly unused in Phenom II, and as a result it's been removed from Bulldozer.

With larger structures feeding into the integer cores, AMD should be able to have an easier time of making use of the integer units than in previous designs. AMD could, in theory, execute more integer operations per core in Phenom II however AMD claims the architecture was typically bound elsewhere.

The Shared FP Core

A single Bulldozer module has a single shared FP core for use by up to two threads. If there's only a single FP thread available, it is given full access to the FP execution hardware, otherwise the resources are shared between the two threads.

Compared to a quad-core Phenom II, AMD's eight-core (quad-module) FX sees no drop in floating point execution resources. AMD's architecture has always had independent scheduling for integer and floating point instructions, and we see the same number of execution ports between Phenom II cores and FX modules. Just as is the case with the integer cores, the shared FP core in a Bulldozer module has larger scheduling hardware in front of it than the FPU in Phenom II.

The problem is AMD had to increase the functionality of its FPU with the move to Bulldozer. The Phenom II architecture lacks SSE4 and AVX support, both of which were added in Bulldozer. Furthermore, AMD chose Bulldozer as the architecture to include support for fused multiply-add instructions (FMA). Enabling FMA support also increases the relative die area of the FPU. So while the throughput of Bulldozer's FPU hasn't increased over K8, its capabilities have. Unfortunately this means that peak FP throughput running x87/SSE2/3 workloads remains unchanged compared to the previous generation. Bulldozer will only be faster if newer SSE, AVX or FMA instructions are used, or if its clock speed is significantly higher than Phenom II.

Looking at our Cinebench 11.5 multithreaded workload we see the perfect example of this performance shuffle:

Cinebench 11.5—Multi-Threaded

Despite a 9% higher base clock speed (more if you include turbo core), a 3.6GHz 8-core Bulldozer is only able to outperform a 3.3GHz 6-core Phenom II by less than 2%. Heavily threaded floating point workloads may not see huge gains on Bulldozer compared to their 6-core predecessors.

There's another issue. Bulldozer, at least at launch, won't have to simply outperform its quad-core predecessor. It will need to do better than a six-core Phenom II. In this comparison unfortunately, the Phenom II has the definite throughput advantage. The Phenom II X6 can execute 50% more SSE2/3 and x87 FP instructions than a Bulldozer based FX.

Since the release of the Phenom II X6, AMD's major advantage has been in heavily threaded workloads—particularly floating point workloads thanks to the sheer number of resources available per chip. Bulldozer actually takes a step back in this regard and as a result, you will see some of those same workloads perform worse, if not the same as the outgoing Phenom II X6.

Compared to Sandy Bridge, Bulldozer only has two advantages in FP performance: FMA support and higher 128-bit AVX throughput. There's very little code available today that uses AMD's FMA instruction, while the 128-bit AVX advantage is tangible.

Cache Hierarchy and Memory Subsystem

Each integer core features its own dedicated L1 data cache. The shared FP core sends loads/stores through either of the integer cores, similar to how it works in Phenom II although there are two integer cores to deal with now instead of just one. Bulldozer enables fully out-of-order loads and stores, an improvement over Phenom II putting it on parity with current Intel architectures. The L1 instruction cache is shared by the entire bulldozer module, as is the L2 cache.

The instruction cache is a large 64KB 2-way set associative cache, similar in size to the Phenom II's L1 cache but obviously shared by more "cores". A four-core Phenom II would have 256KB of total L1 I-Cache, while a four core Bulldozer will have half of that. The L1 data caches are also significantly smaller than Bulldozer's predecessor. While Phenom II offered a 64KB L1 D-Cache per core, Bulldozer only offers 16KB per integer core.

The L2 cache is much larger than what we saw in multi-core Phenom II designs however. Each Bulldozer module has a private 2MB L2 cache.

There's a single 8MB L3 cache that's shared among all Bulldozer modules on a chip. In its first incarnation, AMD has no plans to offer a desktop part without an L3 cache. However AMD indicated that the L3 cache was only really useful in server workloads and we might expect future Bulldozer derivatives (ahem, Trinity?) to forgo the L3 cache entirely as a result.

Cache accesses require more clocks in Bulldozer, due to a combination of size and AMD's desire to make Bulldozer a very high clock speed part...

Introduction The Pursuit of Clock Speed
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  • actionjksn - Thursday, October 13, 2011 - link

    AMD Nailpuller? That was some funny shit right there HA HA HA
  • Spam not Spam - Wednesday, October 12, 2011 - link

    Just skimmed the review; not as awesome as I had hoped for, sadly. That being said, I'm thinking it might well be a nice improvement for the stock, C2D Q6600 in my Dell. I could go Intel, obviously, but... I dunno. I've got an odd fascination with novel things, even if they are rough to begin with. Hell, I've even got a WP7 phone :p
  • wolfman3k5 - Wednesday, October 12, 2011 - link

    Then make sure to get a quality power supply and motherboard to go with it. Also, your power bill will increase, but not directly from the Bulldozer CPU, nope, but from all the heat that it will make... you will need to run your air conditioner which is a power hog.

    /* Patiently waiting for AMD's next gen architecture codenamed "Bendover" */
  • ckryan - Wednesday, October 12, 2011 - link

    Is 'ScrewdOver' next on the roadmap after 'Bendover'? I'll have to look in the official AMD leaked slide repository.

    I still think some intrepid AMD faithful will try BD out just because they're wired that way, and many of the are going to like it. I bet it compares better to Lynnfield than Sandy Bridge... Except Ivy Bridge is closer in the future than SB's launch is in the past. This could be an interesting and relevant product after a few years, but the need is dire now. AMD is going to kill off the Phenom II as fast as possible.
  • themossie - Wednesday, October 12, 2011 - link

    Bendover -> ScrewdOver -> Screwdriver (I'll bring the OJ) -> Piledriver.
    Courtesy of numerous internal leaks at AMD.
  • themossie - Wednesday, October 12, 2011 - link

    My apologies, didn't realize Piledriver was real.
  • bill4 - Wednesday, October 12, 2011 - link

    AKA, the reason all of us who are commenting are reading this review. Gaming performance. And AMD chose not to even compete there. Bunch of monkey overs at AMD CPU engineering?

    It's now a non starter in the enthusiast market.

    I've often though recently that AMD (or any manufacturer really, but AMD as a niche filler would be a more obvious choice given their market position) would do well to try to position itself as the gamers choice, and even design it's CPU's to excel in gaming at the expense of some other things at times. I really suspect this strategy would lead to a sales bonanza. Because really the one area consumers crave high performance is pretty much, only gaming. It's the one reason you actually want a really high performance CPU (provided you dont do some sort of specialized audio/video work), instead of just "good enough" which is fine for general purpose desktoping.

    Instead they do the exact opposite with Bulldozer, facepalm. Bulldozer is objectively awful in gaming. Single handedly nobody who posts at any type of gaming or gaming related forum will ever buy one of these. Unbelievable.

    Perhaps making it even more stinging is there was some pre-NDA lift supposed reviewer quote floating around at about how "Bulldozer will be the choice for gamers" or something like that. And naturally everybody got excited because, that's all most people care about.

    Combine that with the fact it's much bigger and hotter than Intel's, it's almost a unmitigated disaster.

    This throws AMD's whole future into question since apparently their future is based on this dog of a chip, and even makes me wonder how long before AMD's engineers corrupt the ATI wing and bring the GPU side to disaster? The ONLY positive thing to come out of it is that at least AMD is promising yearly improvements, key word promising. Even then absolute best case scenario is that they slowly fix this dog in stages, since it's clearly a broken architecture. And that's best case, and assumes they will even meet their schedule.

    Anand lays so much of the blame at clockspeed, hinting AMD wanted much more. But even say, 4.3 ghz Bulldozer, would STILL be a dog in all important gaming, so there's little hope.
  • shompa - Wednesday, October 12, 2011 - link

    I have used many AMD systems. Have deployed 1000 of AMD CPU inside Unix workstations at my old work. I cheer for AMD.
    AMD is going to have a hard time ahead. Selling its fabs to Global foundries was the biggest mistake of them all.

    We are in the post PC world. If Tablets are computers: 2012 20% of PCs will use ARM. This is many lost CPU sales for AMD/Intel.

    I predict that AMD will be gone within 3 years. Maybe someone buys them? After the settlement with Intel, AMD now can transfer its X86 license to the next buyer. (pending Intels approval)

    Maybe Google could buy AMD and build complete computers ?
  • wolfman3k5 - Wednesday, October 12, 2011 - link

    I see two things that might happen to AMD
    1) They will transform in to a GPU manufacturer completely (and of course they will make those silly APUs)
    2) If that damn x86 license is transferable, they could merge with NVidia. Neither of these two companies looks to hot these days, so they might as well work together.
  • philosofool - Thursday, October 13, 2011 - link

    We may be in the "post PC" era, but don't count x86 out. Recent studies indicate there's a corollary to Moore's law that applies to compute power per watt; the study goes back to 1961. This suggests that x86 is only a few years away from running on mobile devices, which is what MS and Intel are betting on. And frankly, it makes sense. Ultimately, I don't want two different things (a mobile device and a PC), I want a PC in my pocket and one on my desk.

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