Transistors

MOSFET Junction Structure / Brews Ohare / CC BY SA

The next inevitable question is how to make a transistor. While there are many other methods of making transistors, it’s best to focus on the one that is used in modern computer chips, namely the metal-oxide-semiconductor field-effect-transistor or MOSFET.

This is a relatively simple design, although there’s a great deal of complexity in its implementation. This type of transistor has four terminals: source, gate, drain, and body. More often than not, the body is shorted to source with a non-rectifying contact (ohmic contact) to eliminate body effect/ground the body. We’ll get back to body effect eventually, but the important part here is to understand source, gate, and drain.

The names are somewhat self-explanatory, but source and drain are the points where the controlled current enters and leaves. The gate is the portion that controls the flow of the current, which means that it's either on or off depending on the voltage (bias) applied to the gate. It's important to keep in mind that current can flow from source to drain or drain to source depending on the type of MOSFET.

MOSFET Functioning Body / Biezl / CC BY SA

There’s more to it than just three terminals though. The actual structure of the MOSFET is critical to understanding why technologies such as HKMG and FinFET exist. In the case of an n-type MOSFET, the source and drain are wells of n-doped semiconductor, with a p-doped semiconductor substrate surrounding the two. In between the two is the gate, which is the metal-oxide-semiconductor portion that the MOSFET is named after.

The gate in a traditional MOSFET is rather simple. On top of the silicon substrate, a layer of silicon dioxide (SiO2) is generated, then a polysilicon or metal gate is placed on top of this SiO2 layer. This structure effectively makes the gate a capacitor, with SiO2 as the dielectric.

Semiconductor Band Bending / Bews Ohare / CC BY SA

Those that have taken some level of introductory physics will know that a capacitor generates an electric field if there is a voltage difference between the plates. While an electric field cannot go through a conductor due to the density of electrons/holes, the same is not true of a semiconductor. Once again, the Fermi level and band diagrams become important.

As a result of the electric field, the silicon of the body near the silicon dioxide has a higher chance of electrons with sufficient energy to become delocalized. This can be seen as band bending in the band diagram, where the conduction band stretches down past the Fermi level. Because the Fermi level is the total chemical potential of electrons, this means that it is much more likely for electrons to jump the band gap between the valence band and the conduction band. However, this comes at a cost.

As the density of electrons increases, the field effect becomes weaker and weaker. Thus, the band bending decreases until the effect is nonexistent. The point where this happens marks the end of the channel created. As a result of the concentration of free electrons, there is an inversion layer created. The reason why it’s an inversion layer is because in the case of this n-type MOSFET (or NMOS), the p-type body/substrate becomes an n-type substrate within the inversion layer.

MOSFET Functioning / Olivier Deleage & Peter Scott / CC BY SA

As a result of the positive voltage on the gate, the inversion layer becomes a “channel” of sorts, which allows current to flow between source and drain. That’s how an NMOS works to control the flow of current from drain to source using a gate. Since the above photo also shows the regions that a transistor can operate in, it's important to understand that the linear operating mode is where the output current of the transistor is directly proportional with voltage. In the saturation mode, this is no longer true and diminishing returns are seen in current despite increasing voltage until the transistor reaches the maximum possible current. In a CMOS camera sensor this makes it difficult to accurately recover overexposed photos as this saturation mode causes the signal to be clipped, which is why underexposed photos are generally preferable to overexposed ones.

Now let’s look at a PMOS. The same is true, merely reversed. By applying a low voltage to the gate, an electric field pushes away electrons, forming a channel of holes that allows current to flow from source to drain. In the interest of avoiding confusion, we’ll avoid discussion depletion-mode MOSFETs for now although it may be worth revisiting at a later point. This is also because depletion-mode FETs effectively don’t exist in today’s processes.

Inversion With Source-Body Bias / Brews Ohare / CC BY SA

Of course, I mentioned the body effect earlier on but never quite explained what it was. Now that we understand how the system works at a basic level, we can add a bit of complexity in the form of biasing on the body terminal. We talked about how applying a voltage to gate would cause the band structure to change. In the case of applying voltage to the body terminal, the same band-bending occurs and alters the threshold voltage on the gate needed to enter the linear region of transistor operation.

CMOS Logic

So now that we understand (maybe) how transistors work, the real question is how to implement logic using these gates. After all, it’s not immediately clear how controlling the flow of current translates into the sheer amount of possible instructions seen in code. While there are multiple methods to do this, this article will only cover the most popular method. This is known as complementary metal-oxide-semiconductor, or CMOS. The reason why this method of implementing logic is so popular is because of its power characteristics. While other methods have significant amounts of current draw regardless of state, CMOS only requires a significant amount of power while switching. We’ll go over why this is later.

Before I go over CMOS, I'll do a quick introduction to Boolean logic for those that are unfamiliar with the subject. In short, it's possible to take apart almost any statement and turn it into a series of logical operations. These operations are AND, OR, and NOT. While there are more operations than those three, every possible logical operation is possible through the combination of the three. This makes it possible to do math, store input and output, and all the other things we see in computing devices today. There's definitely much more to it, although that's best left for another day.

Now that we've done an extremely basic introduction of Boolean logic, CMOS is rather simple in its rules for implementing such logic. Through these rules, it’s possible to implement every possible logic gate, and we’ll go over the simplest example for CMOS, the NOT gate. CMOS is purely composed of p-type and n-type MOSFETs, with no need for resistors that would generate waste heat. There are only two rules that must be followed to be electrically considered a CMOS circuit:

1. All PMOS transistors must either have an input from the voltage source or another PMOS transistors.
2. All NMOS transistors must either have an input from ground or another NMOS transistor.

Using these two rules it is possible to build all the other gates. For example, the NOT gate simply requires one NMOS and one PMOS. The PMOS is connected to the voltage source and the NMOS to the ground. The gate for both is controlled by a single input, and the output current is also connected together. An example of this circuit diagram can be seen below. I've also included a link for a java applet that simulates this circuit here.

NOT Gate / OpenStax CNX

If the input voltage is high, the NMOS turns on and the PMOS is off. The result is that the output wire is pulled to the ground voltage, which is 0V. This would be measured as a low voltage. If the input voltage on the gate is low, then the PMOS will switch on. The result is that the output wire has a voltage close to Vdd, which is relatively high. If the truth table is written out, we can see that this matches exactly with the truth table for the NOT operation.

Of course, there are multiple other operators. While it might be worth going over for those interested in majoring in electrical or computer engineering, to keep things (relatively) simple we’ll avoid talking through how those circuits work.

Through billions of transistors arranged in the complementary fashion just described, entire CPUs are made. Of course, these aren’t individual pieces. These billions of transistors are on a single package no bigger than the size of a fingernail. For reference, A5X was one of the largest mobile SoCs ever shipped, and its die area is 163 square millimeters. Apple’s A6 SoC is only around 97 square millimeters, or smaller than a square with side length of a centimeter. The question now is how to squeeze all of these transistors into such a small area. To answer that, we must look at the manufacturing process.

Introduction and Semiconductor Physics Manufacturing: From Wafer to Chip
POST A COMMENT

77 Comments

View All Comments

  • danjw - Thursday, October 9, 2014 - link

    I am wondering if we haven't already hit the limits of current technology. TSMC doesn't seem to be able to produce anything more powerful than a SOC for phones and tablets on their 20nm process. While Intel seems to think they will have 14nm desktop and notebook parts out in the second quarter of next year, I wonder if they really will. Right now all we have seen from them at 14nm is similar to what TSMC is able to do at 20nm.

    This really concerns me as far as technology stagnating until the next big thing comes along.
    Reply
  • Homeles - Thursday, October 9, 2014 - link

    There's no end in sight. About a year ago, perhaps a little earlier, the 7 or 5nm nodes were seen as the end of Moore's Law. Advancements have been made since then, though, and scaling past the 5nm node is very likely. 10nm's "recipe" is basically all finished at Intel at this point, with "all" that's left to do at this point being increasing the yields. EUV is making good progress, finally, and should be ready for insertion at Intel's 7nm node (if they skipped it for 10nm, which they likely did).

    14nm has been in production for quite some time now, with Broadwell first landing in tablets later this month. The chances that Broadwell won't make it to the desktop and notebook market around the middle of next year are essentially zero.

    We're still also on schedule to have 450mm wafers introduced by the end of the decade, which would reduce costs by ~30%.

    Even not looking at Intel, TSMC has millions of 20nm-based products on the market right now. 20nm is roughly twice as dense as its 28nm predecessor. It doesn't really make sense to be so skeptical of progress, given that the proof pudding has already been delivered.
    Reply
  • danjw - Thursday, October 9, 2014 - link

    All those 20nm products are not desktop or notebook CPUs or GPUs, which they lead AMD and Nvidia to believe they would be able to do. Intel is way behind its original estimates to get Broadwell out, and that just in table SOCs. Intel wanted badly to get Broadwell parts out for the new school year, then it was Christmas, now it is Q2 of 2015. Yes, I think there is plenty of reason to be skeptical. Reply
  • EMM81 - Monday, October 13, 2014 - link

    Your facts are all incorrect...If you can produce an SOC you already have all of the capability to produce GPU's or CPU's since it has logic, SRAM and graphics components already. Broadwell parts are already in the hands of vendors NOW and are being sold this year and they are not SOC's they are low power full core chips. 14nm Broadwell chips are in no way equivalent to 20nm TSMC chips. A fab can use the additional capability of a new node in different ways. They can reduce density to make chips cheaper to make, increase performance, decrease power and all of these things will be done in different ratios depending on the product. You need to work on detailed reasoning and apples to apples comparisons. Reply
  • errorr - Thursday, October 9, 2014 - link

    The problem is that the only real advancements are more expensive per transistor and I doubt they will change.

    The great thing about process shrinks is that it reduces the cost per transistor.

    Also I doubt EUV will ever work. It has been almost ready and a couple years away for a decade. Tell me when you don't need MW levels of power to get usable light to a wafer and maybe I will consider it.

    450mm wafers have also been just a couple years away for at least 15 years. I'll believe the 2020 hype when I actually see it.

    The way to the next node is easy and everyone knows they can use triple patterning. Nobody wants that because of the expense is huge already and every single circuit would have to be redrawn due to limitations on the pokygons.

    I don't know what's next but the only people expecting EUV to pan out are the people who have spent billions trying to make it work and failing.
    Reply
  • ShieTar - Friday, October 10, 2014 - link

    EUV is not "almost ready", it has been commercially available for 2 years now.

    http://www.zeiss.com/semiconductor-manufacturing-t...
    Reply
  • Khenglish - Thursday, October 9, 2014 - link

    The problem with smaller processes is not physically producing them. The problem is that they start getting slower than larger processes. This is due to 2 reasons.

    1. Narrower, more resistive interconnects.
    2. Increase in channel doping levels due to not having enough dopant atoms to form a P-N junction as processes increase.

    1. As process sizes shrink, so do interconnects. Resistance is dependent on cross sectional area and length of the wire. As you shrink a process, the cross sectional area drops at a squared rate, while length drops at a linear rate. The end result is that wires become linearly more resistive as the process shrinks. Keeping wire length down due to resistance is also a big reason why individual core transistor counts have not been going up significantly. The cores need to stay small to keep the wire length down. Repeaters to boost current drive ability on long wires has been around starting at around 90nm.

    2. If you want a 10nm process, you probably have a gate length of 10nm. The volume of a 10nm cube is 10^-18 cm^-3. High doping levels are those above around 10^17 atoms per cm. If we take a high doping level of say 10^18 atoms per cm, then we have only one single dopant atom in the entire channel region of the transistor. This means that if you are one atom off, you lose a transistor, which is difficult not to do with over 1B transistors in a microprocessor. You can dope up to around 10^21 cm^-3, but then your electron and hole mobility are terrible. Mobility is directly proportional to how much current a transistor can push, so as mobility drops performance drops. See this link for what happens to mobility as dopant levels increase.

    http://ecee.colorado.edu/~bart/book/mobility.gif
    Reply
  • abufrejoval - Saturday, October 11, 2014 - link

    From what I read the problem isn't as much phyiscal or technical feasability as economical viability: Moore's law was mostly about the ability to deliver more power at a lower price for the end consumer pushing the technology. Now the economical yields of process shrinks are diminishing to the point where further shrinks won't pay for themselves. Reply
  • DanNeely - Thursday, October 9, 2014 - link

    If you're also interested in how simpler transistors are made; hack-a-day's hosted a video lecture from someone who was producing chips with a handful of transistors on them in her home lab a few years ago.

    http://hackaday.com/2010/03/10/jeri-makes-integrat...
    Reply
  • anexanhume - Thursday, October 9, 2014 - link

    Graphene isn't dead in the water. There are ways to create a bandgap, for example using bilayer graphene and introducing a gap via electric fields or doping.

    http://www-als.lbl.gov/index.php/contact/56-bilaye...

    Then you can take advantage of its remarkable carrier mobility. Mass production remains a huge issue, and I also have concerns about its effect on living creatures and the environment. http://www.gizmag.com/graphene-bad-for-environment...
    Reply

Log in

Don't have an account? Sign up now