MOSFET Junction Structure / Brews Ohare / CC BY SA

The next inevitable question is how to make a transistor. While there are many other methods of making transistors, it’s best to focus on the one that is used in modern computer chips, namely the metal-oxide-semiconductor field-effect-transistor or MOSFET.

This is a relatively simple design, although there’s a great deal of complexity in its implementation. This type of transistor has four terminals: source, gate, drain, and body. More often than not, the body is shorted to source with a non-rectifying contact (ohmic contact) to eliminate body effect/ground the body. We’ll get back to body effect eventually, but the important part here is to understand source, gate, and drain.

The names are somewhat self-explanatory, but source and drain are the points where the controlled current enters and leaves. The gate is the portion that controls the flow of the current, which means that it's either on or off depending on the voltage (bias) applied to the gate. It's important to keep in mind that current can flow from source to drain or drain to source depending on the type of MOSFET.

MOSFET Functioning Body / Biezl / CC BY SA

There’s more to it than just three terminals though. The actual structure of the MOSFET is critical to understanding why technologies such as HKMG and FinFET exist. In the case of an n-type MOSFET, the source and drain are wells of n-doped semiconductor, with a p-doped semiconductor substrate surrounding the two. In between the two is the gate, which is the metal-oxide-semiconductor portion that the MOSFET is named after.

The gate in a traditional MOSFET is rather simple. On top of the silicon substrate, a layer of silicon dioxide (SiO2) is generated, then a polysilicon or metal gate is placed on top of this SiO2 layer. This structure effectively makes the gate a capacitor, with SiO2 as the dielectric.

Semiconductor Band Bending / Bews Ohare / CC BY SA

Those that have taken some level of introductory physics will know that a capacitor generates an electric field if there is a voltage difference between the plates. While an electric field cannot go through a conductor due to the density of electrons/holes, the same is not true of a semiconductor. Once again, the Fermi level and band diagrams become important.

As a result of the electric field, the silicon of the body near the silicon dioxide has a higher chance of electrons with sufficient energy to become delocalized. This can be seen as band bending in the band diagram, where the conduction band stretches down past the Fermi level. Because the Fermi level is the total chemical potential of electrons, this means that it is much more likely for electrons to jump the band gap between the valence band and the conduction band. However, this comes at a cost.

As the density of electrons increases, the field effect becomes weaker and weaker. Thus, the band bending decreases until the effect is nonexistent. The point where this happens marks the end of the channel created. As a result of the concentration of free electrons, there is an inversion layer created. The reason why it’s an inversion layer is because in the case of this n-type MOSFET (or NMOS), the p-type body/substrate becomes an n-type substrate within the inversion layer.

MOSFET Functioning / Olivier Deleage & Peter Scott / CC BY SA

As a result of the positive voltage on the gate, the inversion layer becomes a “channel” of sorts, which allows current to flow between source and drain. That’s how an NMOS works to control the flow of current from drain to source using a gate. Since the above photo also shows the regions that a transistor can operate in, it's important to understand that the linear operating mode is where the output current of the transistor is directly proportional with voltage. In the saturation mode, this is no longer true and diminishing returns are seen in current despite increasing voltage until the transistor reaches the maximum possible current. In a CMOS camera sensor this makes it difficult to accurately recover overexposed photos as this saturation mode causes the signal to be clipped, which is why underexposed photos are generally preferable to overexposed ones.

Now let’s look at a PMOS. The same is true, merely reversed. By applying a low voltage to the gate, an electric field pushes away electrons, forming a channel of holes that allows current to flow from source to drain. In the interest of avoiding confusion, we’ll avoid discussion depletion-mode MOSFETs for now although it may be worth revisiting at a later point. This is also because depletion-mode FETs effectively don’t exist in today’s processes.

Inversion With Source-Body Bias / Brews Ohare / CC BY SA

Of course, I mentioned the body effect earlier on but never quite explained what it was. Now that we understand how the system works at a basic level, we can add a bit of complexity in the form of biasing on the body terminal. We talked about how applying a voltage to gate would cause the band structure to change. In the case of applying voltage to the body terminal, the same band-bending occurs and alters the threshold voltage on the gate needed to enter the linear region of transistor operation.

CMOS Logic

So now that we understand (maybe) how transistors work, the real question is how to implement logic using these gates. After all, it’s not immediately clear how controlling the flow of current translates into the sheer amount of possible instructions seen in code. While there are multiple methods to do this, this article will only cover the most popular method. This is known as complementary metal-oxide-semiconductor, or CMOS. The reason why this method of implementing logic is so popular is because of its power characteristics. While other methods have significant amounts of current draw regardless of state, CMOS only requires a significant amount of power while switching. We’ll go over why this is later.

Before I go over CMOS, I'll do a quick introduction to Boolean logic for those that are unfamiliar with the subject. In short, it's possible to take apart almost any statement and turn it into a series of logical operations. These operations are AND, OR, and NOT. While there are more operations than those three, every possible logical operation is possible through the combination of the three. This makes it possible to do math, store input and output, and all the other things we see in computing devices today. There's definitely much more to it, although that's best left for another day.

Now that we've done an extremely basic introduction of Boolean logic, CMOS is rather simple in its rules for implementing such logic. Through these rules, it’s possible to implement every possible logic gate, and we’ll go over the simplest example for CMOS, the NOT gate. CMOS is purely composed of p-type and n-type MOSFETs, with no need for resistors that would generate waste heat. There are only two rules that must be followed to be electrically considered a CMOS circuit:

1. All PMOS transistors must either have an input from the voltage source or another PMOS transistors.
2. All NMOS transistors must either have an input from ground or another NMOS transistor.

Using these two rules it is possible to build all the other gates. For example, the NOT gate simply requires one NMOS and one PMOS. The PMOS is connected to the voltage source and the NMOS to the ground. The gate for both is controlled by a single input, and the output current is also connected together. An example of this circuit diagram can be seen below. I've also included a link for a java applet that simulates this circuit here.

NOT Gate / OpenStax CNX

If the input voltage is high, the NMOS turns on and the PMOS is off. The result is that the output wire is pulled to the ground voltage, which is 0V. This would be measured as a low voltage. If the input voltage on the gate is low, then the PMOS will switch on. The result is that the output wire has a voltage close to Vdd, which is relatively high. If the truth table is written out, we can see that this matches exactly with the truth table for the NOT operation.

Of course, there are multiple other operators. While it might be worth going over for those interested in majoring in electrical or computer engineering, to keep things (relatively) simple we’ll avoid talking through how those circuits work.

Through billions of transistors arranged in the complementary fashion just described, entire CPUs are made. Of course, these aren’t individual pieces. These billions of transistors are on a single package no bigger than the size of a fingernail. For reference, A5X was one of the largest mobile SoCs ever shipped, and its die area is 163 square millimeters. Apple’s A6 SoC is only around 97 square millimeters, or smaller than a square with side length of a centimeter. The question now is how to squeeze all of these transistors into such a small area. To answer that, we must look at the manufacturing process.

Introduction and Semiconductor Physics Manufacturing: From Wafer to Chip
Comments Locked


View All Comments

  • Kidster3001 - Wednesday, October 29, 2014 - link

    Modern chips are connected with a C4 process (Controlled Collapse Chip Connect) The interconnect side is down, the bulk side is up. The heatsink is touching the back of the wafer.
  • nand - Friday, October 10, 2014 - link

    when i was 18 and in college i couldn't get head my over this stuff - after few years of growing up it makes perfect sense...
  • sammycbvb - Friday, October 10, 2014 - link

    Awesome article. I was waiting for a simplified explanation of Semiconductors and you've delivered.
  • GT69 - Friday, October 10, 2014 - link

    Great article for this old EE whose career was mostly in sales and marketing, but who has had a great love for PC's since the days of Apple II and CP/M. Nice that someone has taken the time and effort to give this generalized explanation even if some of the nit-pickers quibble over a typo or some specific detail. Until one has had to actually produce such a piece he/she should refrain from too much criticism. Easy and quick it ain't! Kudos...
  • Dr.Neale - Saturday, October 11, 2014 - link

    After many years of editing scientific / technical / medical journal articles, I tend to see the structural details as well as the informational content.

    To me, a typo is like a dead pixel. If it can be removed, it makes the image or storyline that much more immersive and enjoyable to behold.

    The purpose is aiding the author in polishing the article to perfection, not fault-finding or nit-picking.

    Like many tech enthusiasts, an editor brings a passionate pursuit of excellence to his craft and to his team.

    Like many other commenters here, I see myself as making a small contribution, from time to time, to the AnandTech team.
  • Dr.Neale - Saturday, October 11, 2014 - link

    P.S. I have also authored or coauthored numerous articles (and a textbook chapter) in the fields of medical physics and medical imaging, including invited review articles.

    So I offer my appeciation and congratulations to Josh Ho for gifting us with an article of such surpassing excellence.
  • dew111 - Friday, October 10, 2014 - link

    This was a good review of my semiconductor physics course. But with less math :)
  • Arnulf - Friday, October 10, 2014 - link

    Very nice technical article, unlike the usual consumerist Apple et al chaff that has swamped this site as of lately!
  • Senti - Friday, October 10, 2014 - link

    Exactly my thoughts! It's really sad to see how level of this site has dropped significantly over years due to caring for more mindless crowd; certain reviewers doesn't bother to actually understand what they are reviewing and just pushing for faster time to post and more numbers (that are by large part are quite unrelevant).

    But articles like this show that hope is not lost here – great job, would love to see more articles like this.
  • SanX - Friday, October 10, 2014 - link

    This is what puzzling for a long time: the wavelength of ArF laser is 192nm, the feature size of Core M processor is 14nm or 14 times smaller. With NA=1 you can focus into spot of the Airy size equal approximately to wavelength only. Using phase shift trick you can probably drop that size twice to 96nm. Using nonlinearity of photoresist you can drop twice more or to 49nm. My guess is that using titlting of laser (i do not get how it actually works) they can get 24nm. Adding water you can get 24 / 1.33=18nm. How they get 14nm and sometimes even 10nm what Samsung claims with just the optical lithography?

Log in

Don't have an account? Sign up now