Comments Locked

92 Comments

Back to Article

  • Pork@III - Monday, October 17, 2016 - link

    Bravo!
  • azok - Monday, October 17, 2016 - link

    Looks like Intel is going to lose the node advantage for mass production.
  • watzupken - Monday, October 17, 2016 - link

    What I understood is that the 14nm that Intel is using is different from what the rest of the industry is claiming. Unfortunately, I am not so savvy with the technicalities.
  • azok - Monday, October 17, 2016 - link

    I got you, but my suspicion was bolstered after going through this.
    http://www.fool.com/investing/general/2015/05/18/h...
  • ddriver - Monday, October 17, 2016 - link

    Well, from the looks of it, samsung's fins are as thin as intel's fins, but samsungs transistors apparently require 3 fins, spreading the entire transistor size to about what intel has with two fins at 22 nm. Process is not just a number, it is a "feature size" number, but it is more important how features are put together to form functional components. The more fins you have the more "contact area" and the better the transistor characteristics. Samsung's process might not really be inferior in terms of feature size, but it might be inferior in terms of material properties, thus requiring 50% more fins to achieve satisfactory transistor performance. It also looks like samsung might actually have better topology, that is physically more accurate feature formation.
  • Toss3 - Monday, October 17, 2016 - link

    They've also modified it after that article was written, so it could be that it has gotten a lot better: https://news.samsung.com/global/samsung-announces-...
  • Anato - Monday, October 17, 2016 - link

    There isn't much point comparing manufacturing feature size as there are tons of other stuff that will affect final product. More important, but harder to compare is the final product and its performance, power consumption and price (PPP). Thats what matters, not the feature size, which is only loosely connected to PPP.
  • azok - Monday, October 17, 2016 - link

    Samsung's ability to get the new process ready in relatively less timeframe is worth a pat. Though Intel announced their 10 nm strategy last year, their red-tapism will surely result in delayed implementation. They should try to see what's happening in their rivals' camp. A lot had changed every since rampant Android and parties took over the world.
  • name99 - Monday, October 17, 2016 - link

    Just FYI, Samsung's and TSMC's timelines for 10nm are pretty much the same.
    It seems like the A10X will ship on TSMC 10nm, likely Q1 2017, maybe very beginning of Q2.

    TSMC also has very aggressive plans for 7nm; certainly the plan right now is for risk production early next year, and likely the A11X in Q1 2018. Then the plan of record is a breather for a 7nm+ in 2019 and 5nm shipping in 2020.
    I haven't seen what Samsung has to say, but I imagine their plans are essentially the same, with maybe 6months or so difference for various milestones.
  • witeken - Tuesday, October 18, 2016 - link

    See EETimes: Samsung seems to plan to skip immersion 7nm and directly use EUV at 7nm. This to me seems quite a dangerous move because Samsung's timing at 7nm is entirely dependent on ASML. Especially because EUV is still nowhere near economic viability. For comparison, Intel plans their 7nm in 2020 and is still developing an immersion alternative for it. Just in case.
  • witeken - Tuesday, October 18, 2016 - link

    Ehh, Samsung's "10nm" node will be only a meager 1.2x denser than Intel's 14nm (in terms of SRAM density) which launched 2 years ago ;).

    Intel 14nm: 0.0588um2 (regular SRAM)
    Samsung 10nm: 0.049um2 (regular SRAM)

    (There's also high density SRAM, which is 1.6x denser for Samsung, but high density SRAM is in fact not used and just sucks in terms of performance.)
  • psychobriggsy - Tuesday, October 18, 2016 - link

    IIRC Intel's 22nm was Tri-Gate (three fins) at 22nm, meaning that their 22nm transistors were nearly as large as a 28nm planar transistor in practice.

    I think they went down to 2 fins at 14nm however.

    Note that their latest 14+ for Kaby Lake is lower density than their previous 14nm, so they could increase clocks a bit. Whether that means they're tri-gate again, or just longer/wider dual-gate I don't know.
  • witeken - Tuesday, October 18, 2016 - link

    You are misunderstanding Tri-Gate / finFET. Those two names refer to the transistor architecture: it's a 3D transistor that has 3 gates. The number of fins per transistor is entirely up to the SoC designer and can be chosen freely per transistor. Increasing the number of fins increases the drive current (performance). At 14nm, Intel has lowered the variability of their transistors, so they had to use fewer fins per transistor, which gave them an undisclosed density boost.

    The name of the node (22nm, 28nm, etc.) is just a marketing name that does not meaning anything. If you want to compare some characteristic of a node, for instance density, there a specific features or characteristics or feature sizes that you have to compare. A process node is so much more nuanced than a single marketing name. It doesn't does billions to develop a new node for nothing...
  • DanNeely - Monday, October 17, 2016 - link

    In terms of actual feature size, or just branding? I know Intel's 14nm process had significantly smaller features than Samsung's 14 and a larger edge than 14 vs 16 would imply vs GloFo's.
  • Toss3 - Monday, October 17, 2016 - link

    Isn't 10nm FF the same size as the regular 14nm node, as in Intel's 14nm == Samsung's 10nm FF? I remember reading something about how both TSMC's 16nm FF and Global Foundries' 14nm FF were basically just modified 20nm nodes, marketed as being smaller than they actually are.
  • lefty2 - Monday, October 17, 2016 - link

    No. Samsung's 10nm is actaully 10% denser than Intel's 14nm. You can see how the different nodes stack up here: https://www.semiwiki.com/forum/content/6160-2016-l...
    And another thing Intel can call it's node anything it wants to. It simply made a poor choice calling it 14nm from a marketing point of view.
  • Toss3 - Monday, October 17, 2016 - link

    Yeah, but look at Intel's 10nm - 9.5nm, while Samsung's is 12nm (shouldn't it be called 12nm?). Didn't mean that they are exactly the same, but that only a part of samsung's 10nm is actually 10nm. Intel's nodes are, as far as I understand it, "real nodes"; as in actually as small as the name would suggest. Probably a lot more to it than that, and I'd love to learn more about it. Maybe anandtech should do a deep dive into the different nodes?
  • lefty2 - Monday, October 17, 2016 - link

    You don't get it. The node name is a made up label. It's only loosely related to the density. There is nothing in a 10nm node that measures 10nm.
    Also, you seem think Intel is automatically superior to everyone else simply because they have higher density. Intel suffer poor yields because of the aggressive tolerances they use. That's why Intel have to start with small cores on a new node. The yields are too low to manufacture the larger die CPUs.
  • fanofanand - Monday, October 17, 2016 - link

    This isn't entirely accurate, the node label is supposed to reflect at least one feature size correlating to the node label. So a 14nm node should have at least one feature that is at 14nm. It certainly doesn't mean that all features are at that size, but at least one should be. Anandtech actually wrote about this a few years back, so hopefully my memory is serving me correctly.
  • lefty2 - Monday, October 17, 2016 - link

    What I said is correct. On Intel's 14nm node the gate pitch has been measured at ~70nm and fin pitch at ~42nm and that is what defines the density. http://www.extremetech.com/computing/193200-intels...
    There is nothing that measures 14nm. But you are welcome to provide a link to any article that proves there is.
  • fanofanand - Monday, October 17, 2016 - link

    As much as I enjoy being correct (and let me tell you, I do enjoy it) I am wrong on this one. " The phrase "xx nm node" means that the smallest spacing between repeated features on a chip along one direction is xx nm. It does not actually mean that transistors are now xx nm by xx nm. "

    So it's not the feature size it's the minimum distance between features. Of course that does make your statement "there is nothing that measures 14 nm" incorrect as well.

    Source: http://nanoscale.blogspot.com/2015/07/what-do-ibms...
  • p1esk - Monday, October 17, 2016 - link

    As your source article shows, the "node size" is supposed to be the channel length. I think this is still somewhat true for Intel.
  • witeken - Tuesday, October 18, 2016 - link

    No, node name has nothing to do with channel length or any other length.

    Intel 22nm channel length was 28nm. Their 14nm channel length is 20nm, their 90nm channel length was about 45nm.
  • witeken - Tuesday, October 18, 2016 - link

    Incorrect. I don't care what your cute blog says, it is wrong. Go to WikiChip and look at the feature sizes. Feature size are not a secret, at least not all of them :). So please come back if you found something to be 10nm or whatever ;).
  • witeken - Tuesday, October 18, 2016 - link

    Unfortunately, your memory is incorrect. You can search the literature all you want, but I can promise you that you will never find even a single feature to be the length of the node name for ANY node in the past 15 years, let alone any node in the future. It's marketing. TSMC and Samsung 14/16nm have same density as their 20nm, for instance.
  • ViRGE - Monday, October 17, 2016 - link

    That's true for any process though. No process comes online ready to fab massive chips with a reasonable yield.
  • lefty2 - Monday, October 17, 2016 - link

    I don't know about that. TSMC seem to start straight away with big die SoCs. The A10X is ment to be the first 10nm part.
    Also, consider that Intel won't start manufacturing high end CPUs on 10nm until 2018. That's more than a year with poor yields and why they had to introduce a new CPU family, coffee lake.
  • extide - Monday, October 17, 2016 - link

    Yeah but A10X is going to be probably a 150mm^2 part MAX -- that's not a big die part. Polaris 10 is about 300mm^2 or so, GP100 is over 600mm^2, and Intel's Knight's Landing is 683mm^2 -- those are big dies, especially the latter two.
  • psychobriggsy - Tuesday, October 18, 2016 - link

    Well, whilst Polaris 10 is 223mm^2 (not 300), GF's 14nm Foundry Yields are extremely good (0.08 defects per cm^2).

    Another factor is routing - TSMC and GF 14/16 allow 2D routing, which is denser than the 1D routing that Intel use. So whilst Intel's transistors have the capability of being closer together and denser, in practice that cannot happen a lot of the time.

    And after that, another factor is how many metal layers can be made on the finest BEOL scale (20nm for TSMC/GF, 14nm for Intel). Intel IIRC can do 4 1D layers at this scale. GF IIRC can do 8 2D layers for a GPU-oriented design targeting density.

    So as you can see there are so many variable that arguing about the process name is difficult. They all have pros and cons. Intel's biggest Pro was being the first to market by over a year, but that's fading away right now. They still have per-transistor power usage (although TSMC seem to compete looking at Pascal GPUs).
  • witeken - Tuesday, October 18, 2016 - link

    In theory (based on transistor area), Intel's 14nm node is 1.4x denser than Samsung's 2D 14nm node. In practice, it is indeed about 1.4x denser. So the 2D routing's impact is negligible.
  • close - Monday, October 17, 2016 - link

    If there was "nothing in a 10nm node that measures 10nm" we'd already have 5 or 2nm nodes. Maybe even smaller. Don't underestimate the ability with which marketing departments fail to understand technical details. This is why in this particular case all marketing terms are actually tied to an engineering concept: feature size. The node is the smallest feature that you actually have on the die. ...With the obvious and hopefully reasonable approximations.
  • witeken - Tuesday, October 18, 2016 - link

    I'm sorry to disappoint you, but you are a little bit naieve. Node names ARE marketing. They used to be engineering names, but marketing hijacked them. So the rule is to shrink the name by 0.7x every generation. So that's what marketing still does. However, they do this even if the feature size does not in fact shrink by 0,7x. 14nm is the same density as foundries' 20nm.

    So again, please go to Wikichip and find me a feature size that is 14nm. You can't because there is none.
  • name99 - Monday, October 17, 2016 - link

    Even more to the point, if any foundry has higher density, so what? Higher density does not automatically correlate with higher performance, lower cost, or anything else that an end user actually cares about.

    Higher density mattered years ago, when it was a struggle to fit everything we wanted on a single die. But now we have so many transistors we just burn them up with yet another core, or throw in another few MB of cache. What's of interest is either the details that affect price (how many steps required to achieve various functionalities), the details that affect design (whether 2D routing can be used, where double or triple patterning is necessary), and the details that affect performance (precise properties of the transistors, how many metal layers, whether advanced materials or air gaps are available).

    The reason (IMHO) the foundries are so happy to let people know about density is precisely because it is so meaningless --- revealing it is not revealing any secret that actually matters worth a damn.
  • witeken - Tuesday, October 18, 2016 - link

    Completely incorrect. Intel has in fact the highest yields in the industry -- Intel's 22nm is in fact their best yielding node EVER. Stop the FUD, please get your facts straight by using reliable sources.
  • bcronce - Monday, October 17, 2016 - link

    13.3nm is 10% denser than 14nm. Kind of lends credence to Samsung 10nm = Intel 14nm.
  • lefty2 - Monday, October 17, 2016 - link

    It's close, but it's not equal. 10% is 10%
  • Meteor2 - Monday, October 17, 2016 - link

    One exists (Intel) the other is 'announced' (Samsung). That leaves Intel with a rather large advantage.
  • bcronce - Monday, October 17, 2016 - link

    Except when you include arbitrary forms of rounding
  • Cygni - Monday, October 17, 2016 - link

    Those values, especially for future processes that they have no hard data on (like, say, Samsungs 10nm), are pure estimations. At best.
  • lefty2 - Monday, October 17, 2016 - link

    I'm told that they created that table using technical data released by the foundries that specifies the metal pitch etc.
  • witeken - Tuesday, October 18, 2016 - link

    I'm sorry to disappoint you, but they didn't. Well, their are two things here.

    First, for the nodes up to 14nm, they indeed used correct transistor feature sizes. However, for all lower nodes they used estimates that clearly favor TSMC by a huge margin. For instance, they assume TSMC 10nm will have 2.1 density, while Intel 10nm has 1.6x density. Their is no reliable source for both of these numbers, so they are clearly invented. Let alone 7nm or 5nm.

    However, all of this doesn't even matter because the formula they use is just WRONG. If your math is wrong, your output is just worthless.
  • name99 - Monday, October 17, 2016 - link

    The process details are generally pretty well known by now. TSMC, for example, has fabricated working ARM test chips on 10nm. Risk product generally starts about 9 months before products ship; I don't know how things break down, but I imagine it's something like 3 or 4 months of debugging and tweaking what was learned in risk production, then 5 or 6 months of building inventory before the tentpole product (high-end phone or tablet or whatever) launched.

    Point is, at this stage in the game, Samsung (and TSMC) surely know their process details. They've probably released them at conferences. They certainly released them to partners a year or more ago. So they're hardly secret. They don't need to be "guessed".
  • medi03 - Monday, October 17, 2016 - link

    What marketing? Since when is Intel into fab business? (producing 3rd party chips)
  • name99 - Monday, October 17, 2016 - link

    The word you want is not fab business but foundry business.
    Intel has tried to be in the foundry business for some years now, with notable lack of success and no design wins worth cheering over.

    http://www.intel.com/content/www/us/en/foundry/ove...
    https://en.wikipedia.org/wiki/Intel#Opening_up_the...

    Opinions differ as to why they have been unsuccessful and whether that will change. Like all the best arguments, there are very few actual facts available, so everyone involved can believe what they like...
    They're supposed to be manufacturing a custom ARM SoC for LG using their 10nm process. Everything I've read about this is all over the place, the suggestion seems to be (without anyone willing to actually commit to a date) that this part is supposed to "start" next year, with no details as to whether "start" means start the design, start risk production, ship in volume, or ...
  • witeken - Tuesday, October 18, 2016 - link

    NOOOO, I'm sorry for this harsh reaction but do not rely on SemiWiki for information.

    I have analysed their article 1 month ago and when I did the math -- which they cowardly hide behind their formula -- it turns out to be a complete TSMC PR article. For instance, according to them, Intel's 10nm and 7nm will be only 1.6x denser then their predecessor, which is a completely lie (1) because Intel has not formally announced density of 10nm and hasn't even spoken about 7nm and (2) because what they DID say is that they will make up for the longer time between nodes by shrinking more aggressively, so at least 2X.
  • name99 - Tuesday, October 18, 2016 - link

    Like most people here, you're obsessed with density. I think this is misleading for the purposes most of us care about. Let me try to give my best explanation here (corrections welcome).

    Consider the following two pictures:
    https://en.wikipedia.org/wiki/Multigate_device#FIN...
    Look at the picture called "A double-gate FinFET device". This is easy enough to understand. Current flow from source to drain (or the other way round, depending on whether you prefer electrons or positive charge...), in a manner that is controlled by the gate.
    Clearly some dimensions of interest here might be the height of the green fin, the width of the green fin, and the distance between the source and drain. In particular, the distance between source and drain should, presumably, have some correlation to transistor switching time, so shrinking it makes the transistor faster.

    OK, now look at
    http://www.electronics-eetimes.com/news/samsung’s-14-nm-lpe-finfet-transistors/page/0/3

    It takes some time to parse this picture, but the parts to compare with the earlier picture are first look for S and D (corresponding to Source and Drain in the previous picture) then the grey interleaving is the gate. The stuff you see that looks like fins is not actually, the fins are thinner and hidden underneath, you see them indicated by the "Si fin direction" arrows.

    The smallest dimensions that appear visible are the widths of the grey (gate) and white (source + drain) elements. This dimension is, as far as I can tell, then, what is called the gate length, and tends to be around 1.7 to 2x the "node". This is, again as far as I can tell, the most important dimension for transistor performance (insofar as it facilitates higher frequency switching).

    The pitches, then, are the minimum distances between objects [including the width of one of the two objects] (as opposed to the minimum widths of objects). The metal pitch is given as about twice the width, and that seems to track with photo.
    This pitch (ie minimum distance between objects) tracks density more closely, in that it limits how many of various things you can place per square micron, but for transistor performance purposes it's probably less interesting than the gate length.

    We can't see the fins in this photo, but the fins are SUPPOSED to be 2/3 (or thiner) the so called gate length. (Which, remember, is, in this picture, actually the WIDTH of the grey protrusions).
    So I think one could reasonably argue that the fin width (more or less) tracks the node name.

    However the actual fin width in these processes seems to be a secret. Even the academic papers I could find didn't mention it.

    Note that the gate length, important though it is, is not the only determinant of the transistor speed. The material properties matter for all the constituents of the transistor (its source, drain, gate, the metal contacts, and the precise geometry). Also the transistor speed is not the only determinant of SoC speed; the speed at which signals can travel over the wires between transistors, especially transistors some distance from each other, also matters and is generally, if you're prepared to burn the power to run your chip at high frequency, the limiting factor unless you work to deal with it.

    And back to density. That's determined, like I said, not exactly by the size of the smallest objects (presumably the fins) but by the minimum distance between objects, which is a different dimension. It's feasible, for example, to be willing to pay for thin fins and short gate lengths, but not be willing to pay to put them very close together (or what amounts to somewhat of the same thing, not be willing to pay for very narrow metal lines that could connect between transistors that are very close together).

    This all makes more sense when you think of it in terms of manufacturing. Each halving of a critical dimension requires a few more finicky manufacturing steps, so if you can get away with not doing that, you're going to.
  • witeken - Wednesday, October 19, 2016 - link

    I am nof necessarily obsessed with density. I also find the other characteristics of a transistor, which you mention, important. However, I don't like it when people don't know the exact sizes and start guessing around without knowledge or led them lead by node names or other crap.

    Most of your analysis is correct, but I do want to make a few small corrections.

    I would have said the gate length is not the ultimate factor that determines speed or power, but you corrected yourself already :). But it is indeed quite an important feature still. So FYI, Intel's 14nm gate length is 20nm, while both Samsung and TSMC have a gate length a bit higher than 30nm.

    Another factor that is important for speed if the fin height. For Intel, this was 34nm at 22nm and increased to 42nm at 14nm. The foundries are in between those values with 14/16nm: about 37-38nm.

    A last factor that is important for speed and power is the subthreshold slope, which for Intel is 65mV/dec, which is close to the theorectical value of 60mV/dec. If I remember correctly, the slope of a planar transistor is about 100mV/dec.

    Next, the features that you try to describe have a specific name, namely fin pitch, gate pitch and interconnect pitch. The best estimate one can make for the transistor area is gate pitch multiplied by gate length: http://www.extremetech.com/wp-content/uploads/2014...

    Lastly, the fin width is indeed one of the shortest features, but it is pretty much a constant for finFETs, so it does not follow the node names or anything.

    For everyone the fin width is 8nm. This will not changes much if any in the coming nodes.
  • name99 - Wednesday, October 19, 2016 - link

    Pitches are the distance between objects. That's part of my point --- I was interested in the size of objects (information that I found hard to find) not the distances between them.

    Do you have a reference for that fin width of 8nm? I could not find anything definite except three claims in different places:
    - that old-style (two-sided) finFET's required a width of half the gate length
    - that tri-gate finFETs (which everyone now uses) required a width of equal to the gate length and
    - that finFETs (no distinction as to trigate or not) required a width of 2/3 the gate length.

    As for fin height, TSMC have demoed chips that use variable fin height (more precisely the process offers two fin heights, and you can use the taller fins where you need larger currents). The advantage was that density improved quite a bit for some structures because locations that had needed two fins could be replaced with a single taller fin. (Of course this is always modulo issues like assuming the wiring can then be made as dense as needed...)
    As always, who knows when that will make it into production. But it certainly suggests that they are on Intel's track and (as always, I guess) looking not just for the performance advantage, but for a level of flexibility beyond what Intel tends to offer.
  • witeken - Wednesday, October 19, 2016 - link

    http://www.intel.com/content/dam/www/public/us/en/...

    It's right there in the Abstract.
  • name99 - Wednesday, October 19, 2016 - link

    Thanks for the reference. Looks very interesting.
  • zodiacfml - Tuesday, October 18, 2016 - link

    Not yet, but it is getting closer. Intel's 10nm will be a match for 7nm of these foundries.
    Intel seems to be taking their time as they don't seem to desire this market, for now, until entry-level PCs starts using ARM than Atom based CPUs.
  • witeken - Tuesday, October 18, 2016 - link

    Intel's 10nm will be about 1.6x denser than Samsung or TSMC's "10nm",

    PLUS, it could be significantly higher performance.
  • jjj - Monday, October 17, 2016 - link

    "or other TSMC customers who have to wait till next year for 10FF"

    That's not true. It's hard to be sure how each ramps and who's first to market but TSMC's 10nm has been transferred from R&D to production in the third quarter. They will ship in Q1 and we'll see ...
    Claims of production start are relative and cycle times are long so LSI will likely not ship anything this year.
    The timing of the ramp also depends on the customer's schedule. it's not about when you can make it but about when the customer needs it. Apple will likely need 10nm for ipad and maybe Mac in March-April. Mediatek should be the first TSMC customer to go 10nm and likely in a rush to show phones at MWC. Huawei , if they have a new high end SoC on 16ff next month, might not be in a hurry to go 10nm and can afford to wait a few moths.

    Last year the announcement came long after production started considering that the S7 hit retail in mid March. This year Samsung needs to change the conversation from the Note 7 disaster so they put out any press releases they can.
  • Andrei Frumusanu - Monday, October 17, 2016 - link

    Apple will likely be first however A10X volume might not be that big so wouldn't be all that indicative, agree that MediaTek seems to be the larger 10nm volume client for the first half of the year but we don't know when exactly they are expecting devices. We know that SLSI and Qualcomm be be shippings in millions by March so that's at least definitely a full quarter advantage.
  • jjj - Monday, October 17, 2016 - link

    MTK hasn't disclosed a precise timing and first half 2017 doesn't mean middle. Time to market matters so it's hard to imagine that they'll miss MWC if nothing goes wrong.
    As for Samsung and Qualcomm how do you know a timing and lets use devices in retail timing since from shipping to retail the gap can differ. Samsung is rumored to launch at MWC so similar schedule to this year. Granted, last year only Xiaomi and Samsung had SD820 devices in retail before April. Hard to say if it's better next year, will depend on how Samsung ramps 10nm, they could be capacity constrained.
    Qualcomm also needs more volume than MTK as X30 won't lead in perf and chances are Samsung has priority. If Qualcomm ships a first wave of 10 million units, it's all S8, if MTK ships 10 million units , it would be to a bunch of customers.

    Anyway, we assume about both but we don't really know yet who's gonna be first to market.
  • Andrei Frumusanu - Monday, October 17, 2016 - link

    The X20 vastly missed the better first half of the year so I don't believe X30 will do that much better, some reports say devices by July. The S8 is pretty much guaranteed to be retail by end of March in high volume. Also I meant MediaTek being the larger 10nm TSMC volume client until the A11, obviously they're not competing for volume against Qualcomm.
  • jjj - Monday, October 17, 2016 - link

    X20 wasn't aimed at high end and had no direct competitor as it was between SD65x and 820.
    Here the timing matters a lot more as it is a much larger investment and A73@ at least 2,8GHz paired with a 200+ GFLOPS Imagination GPU is pretty compelling. Ofc if MTK ends up needing a respin ,they'll be late.

    The volume comparison was about retail availability. S8 could suck all the SD supply at first so , at identical timing, that favors MTK. TSMC is also great at ramping production.
    After all, lest say they get 500 good dies per wafer. With 10k wafer starts per month that's 5 million SoCs per month, 15 million per quarter. Someone like Xiaomi or LeEco would need 2-5million per quarter. 500k to 1 million initial supply. TSMC was planning to ramp 10nm to 200k wafer starts per quarter so they really need to ramp it fast and peak in Q3- Q4 as 10nm is short lived.
  • name99 - Monday, October 17, 2016 - link

    iPad volumes are larger than you think...
    The easy way to remember Apple volumes (order of magnitude) is they manufacture a million
    - iphones/business day
    - ipads per week
    - watches per month (perhaps going to increase to million watches/fortnight over the next year?)
    - macs/quarter

    So about a fifth as many iPads as iPhones. That's still ~50 million a year...
  • jjj - Tuesday, October 18, 2016 - link

    Not all ipads get refreshed at the same time and there are always older models still in retail.
    For example, if there is a spring refresh for just the Pro models, that's maybe 5-6 million units in the first full quarter of availability.The die is bigger than in an iphone but it's still not that much in terms of wafer starts.
  • name99 - Tuesday, October 18, 2016 - link

    Perhaps. Truth is we don't really know the sales by model breakdown, and we don't know Apple's plans here. They may, for example, plan to release a full range of Pro models this time round, with an A10X in 7.9, 9.7, and 12.9 inch sizes, and having an A10X Pro model in the mini size might substantially jump sales?
  • jjj - Wednesday, October 19, 2016 - link

    Even so the older models remain in retail and volumes for the new models would not increase by a lot unless the design gets a major upgrade.
    The 12 inch ipad sold poorly and the 9.7 inch Pro failed to boost their units.It's very obvious if you look at their quarterly sales in the least few quarters.
    However, a spring upgrade for the entire line is unlikely as it makes more sense to do some upgrades now ahead of the winter holidays.
    Macs could go ARM , maybe just the Air first and that would add 1-2 million units.Someone recently spotted ARM support in OS X so Apple is at least pondering a shift.
  • kitty4427 - Monday, October 17, 2016 - link

    Maybe Samsung should start manufacturing desktop CPUs so that Intel actually has a competitor.
  • Toss3 - Monday, October 17, 2016 - link

    Not sure how lucrative that would be considering they don't have a license for x86. AMD are already using Samsung's nodes by using Global Foundries, as they license theirs from Samsung (at least the 14nm FF node).
  • TheinsanegamerN - Monday, October 17, 2016 - link

    That would either require a x86 license or desktops to move to ARM. Both are about as likely.
  • sypack - Monday, October 17, 2016 - link

    Recently there was a rumour that Samsung would buy AMD.
  • A5 - Monday, October 17, 2016 - link

    The long time rumor is that AMD's x86 license gets terminated if they are bought out.
  • looncraz - Monday, October 17, 2016 - link

    That's a fact - not rumor.
  • vladx - Monday, October 17, 2016 - link

    It makes no sense for Samsung to buy AMD, the only real buyer option would be Apple since they need x86 for their Macbooks.
  • boozed - Monday, October 17, 2016 - link

    Hurr durr does it catch fire

    Sorry
  • Michael Bay - Monday, October 17, 2016 - link

    They just needed to trumpet SOMETHING after exploding phones fiasco. Expect it to be as much 10nm as their 14nm was a couple years before.
  • SydneyBlue120d - Monday, October 17, 2016 - link

    I wonder who will use the new process other than Samsung itself and Qualcomm?
  • fanofanand - Monday, October 17, 2016 - link

    For years we have been pining for AMD to step up their game to give Intel some competition, but it looks like it will be Samsung instead. AMD might still push them hard with Zen but Intel is suddenly awash in competition where it previously had none. I don't think now is a good time to be long in Intel stock.
  • looncraz - Monday, October 17, 2016 - link

    AMD is partnered with Samsung and GloFo for production.

    AMD has stated they are jumping to 7nm GloFo, though, so it's unclear if they will use Samsung's 10nm or if GloFo will license it.
  • fanofanand - Monday, October 17, 2016 - link

    AMD is partnering with TSMC and has to pay GloFo for each chip produced at TSMC. The agreement itself is very interesting. GloFo will license Sammy's 10 nm tech, I think the side agreement with TSMC was for Vega, and to put a spur in GloFo's behind to get them working harder to catch up.
  • iwod - Monday, October 17, 2016 - link

    Triple Patterning in Samsung 10nm??!!! Wow, that means Samsung is ahead of the game? If i remember TSMC only goes to Triple Pattering in 7nm.

    And this means it is likely to be the first time in the last two decade Intel has lost in leading edge Fab tech for real ( Not node numbering ). Although Intel 10nm should be out sometimes in 2017 too.
  • vladx - Monday, October 17, 2016 - link

    It's not that others can't use triple patterning it's just that it's very expensive and Samsung can afford it with very few risks.
  • witeken - Tuesday, October 18, 2016 - link

    You are unfortunately incorrect.

    First, you are incorrect that Intel hasn't lost its manufacturing lead in two decades. The most recent time was at 28nm, which launched in AMD GPUs in January 2012, which is in fact denser than Intel's 32nm, which was only followed by their 22nm in April.

    Second, triple patterning does not mean anything. The only thing it means is that Samsung's 10nm will be significantly costlier to manufacture than Intel's 14nm.

    So here's a fun fact: Samsung's SRAM cell size is only 1.2x bigger than Intel's 14nm SRAM size which is made with double patterning.

    So Samsung's "10nm" will only be modestly denser than Intel's 14nm. Intel's 10nm will be about 1.6x denser than Samsung's 10nm.

    So there you go.
  • The_Assimilator - Monday, October 17, 2016 - link

    All these people saying Intel is behind make me laugh. There's a reason they're nicknamed Chipzilla.
  • fanofanand - Monday, October 17, 2016 - link

    The reason is that they were (for the better part of history) the leading edge fabricator of semiconductors. That is changing, and changing rapidly. Anyone saying Intel's lead has not diminished makes ME laugh. If you don't think there is panic at Intel over the recent blunders you are crazy. Mobile was a dead-end where they wasted BILLIONS, IBM and ARM are elbowing in on the server space, AMD has a compelling server chip coming, and now Samsung is eating away at their foundry leads. Chipzilla is crashing down to earth very quickly, and I suspect their margins will come down with it.
  • Michael Bay - Tuesday, October 18, 2016 - link

    >Mobile was a dead-end where they wasted BILLIONS
    Their billions to waste, not mine. Experience in lowpower is what they got out of it.
    >IBM and ARM are elbowing in on the server space
    In their dreams they surely do.
    >AMD has a compelling server chip coming
    We hear that for how many years exactly now?
    >Samsung is eating away
    Until it starts exploding. Or touting 14nm as 10.
  • witeken - Tuesday, October 18, 2016 - link

    Sorry, but your post is just based on emotions. Intel will have in 2016 their highest revenue ever with more than $55B.

    Secondly, your knowledge of history is not impeccable. Intel hasn't had a leasing edge position for "the better part of history". They only had a decent advantage from around 2005, with Tick-Tock. But even then it hasn't always been a pure lead, sometimes TSMC has been a little denser, but then maybe a few months later Intel already had their new node, etc.
  • AnotherGuy - Monday, October 17, 2016 - link

    Some people here are saying only 10% denser, in the article it says 30% increase in area efficency... doesnt that mean 30% denser?
  • psychobriggsy - Tuesday, October 18, 2016 - link

    10% denser than Intel's 14nm.

    The first time in a long time that Intel has fallen behind in transistor layer theoretical density - even if it's only for about 9 months (after the 10nm SS chip comes out) until Cannonlake comes out.

    Given Samsung's 2D BEOL metal routing versus Intel's 1D, the achieved density is likely more than 10% compared to Intel's 10nm, but people often don't consider this.
  • witeken - Tuesday, October 18, 2016 - link

    The last time Intel lost its density lead was in fact in 2014: Apple announced their 20nm A8 chip one day before Intel announced 14nm Broadwell-Y, so not all that long ago...

    The time before that was in 2012: in January AMD launched HD7000 on 28nm, in April Intel launched 22nm.

    So now it will be similar. In April or so (it takes 3 months to manufacture a chip) Samsung S8 and Apple A10X will come out, about half a year later Intel's 10nm will be launched --- Intel's 10nm has in fact about a 1.6x higher density than Samsung/TSMC "10nm".
  • witeken - Tuesday, October 18, 2016 - link

    With the 30% denser, Samsung is referring to the size of their SRAM, which has shrunk from 0.070um2 to 0.049um2.
  • Amandtec - Monday, October 17, 2016 - link

    If this is true Samsung can expect explosive growth in unit shipments next year.

    Too soon?
  • fanofanand - Monday, October 17, 2016 - link

    Where are you getting the correlation between node feature size and units shipped?
  • fanofanand - Monday, October 17, 2016 - link

    Nevermind, I didn't catch the lame puns. *sigh*
  • RU482 - Monday, October 17, 2016 - link

    sounds like the kind of thing that set demand for their phones on fire
  • 0iron - Monday, October 17, 2016 - link

    Andrei is back? Looks like you're in hibernation :)
    Is 8890/820 deep dive still in the plan?
  • sseemaku - Tuesday, October 18, 2016 - link

    Seems like everybody got bought into the marketing. Historically, each process node brought 50% scaling or double the transistor count in given area. But no foundry is following this anymore. In samsung's case, the scaling is 30% but called 10nm. Good marketing.
  • witeken - Tuesday, October 18, 2016 - link

    Correct, although even the 50% is not usually reached. It varies a lot from node to nodes. In the last nodes however, at 14nm and 10nm and likely again at 7nm, Intel has indeed shrunk or will shrink by about 2x density. For comparison, TSMC has already said their 7nm will shrink by 1.63x.

Log in

Don't have an account? Sign up now