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  • Sychonut - Wednesday, July 31, 2019 - link

    But, BUT, and hear me out on this one, the real question is can it compete with Intel's 14nm+++++++?
  • PeachNCream - Wednesday, July 31, 2019 - link

    Shhh! You're going to invoke HStewart.
  • regsEx - Wednesday, July 31, 2019 - link

    Probably Intel should have do the same as Samsung and TSMC.
    Rename 14+ to 12 nm
    Rename 14++ to 10 nm

    Rename 10 to 7 nm
    Rename 10+ to 6 nm

    Rename 7 to 5 nm
  • regsEx - Wednesday, July 31, 2019 - link

    No, wait. Intel 7 nm as dense as TSMC 3 nm, so 10++ would be 5 nm and 7 would be 3 nm.
  • extide - Wednesday, July 31, 2019 - link

    Yeah, exactly all these guys are doing process revs, just calling it differently, but it's really the SAME THING!
  • JSS - Sunday, September 29, 2019 - link

    Are the transistors in the 7LPP not 7nm in size? And 6nm in size in the 6LPP, and 5nm in size in the 5LPE, and 4nm in size in the 4LPE?
  • Teckk - Wednesday, July 31, 2019 - link

    Do we know Intel's EUV plan? Does it start with its 7nm? I'm guessing Samsung and TSMC have been pretty vocal in terms of EUV but Intel is surprisingly not. Won't it help Intel considering it manufactures more complex chips compared to other foundries? (IoT, memory, x86 client, server etc.)
  • Teckk - Wednesday, July 31, 2019 - link

    Can't edit... But yeah, seems pretty aggressive from Samsung, both the claims and the marketing/naming.
  • Kevin G - Wednesday, July 31, 2019 - link

    Samsung is being aggressive here now that EUV tools are available. Though their naming schema is heavy on the marketing. Still, they’ll be ahead of Intel for a bit.

    Thus far, I have yet to see what I would call a complex chip at 10 nm class or below in volume. The closest would be Vega 20 at 331 mm^2. The previous generation of nodes set a new record at 818 mm^2. Intel could start producing large dies before their competitors but everyone seems to be going in the direction of chiplets and advanced packaging technologies to work around yields.
  • saratoga4 - Wednesday, July 31, 2019 - link

    >everyone seems to be going in the direction of chiplets and advanced packaging technologies to work around yields.

    With 2nd gen EUV, the reticle limit drops to ~400 mm^2, so vendors are getting ready for the end of large die parts.
  • Yojimbo - Thursday, August 1, 2019 - link

    The reticle will still be 6", it's the on-wafer field size that drops due to using a half-field in order to keep the angles of the light down. If they switched to a larger mask (9 inches) they could maintain the same maximum die size but I don't think that's what they plan to do. I guess that would be very expensive? Anyway, all that is 4 years out at least. Semiconductor companies have been researching multi-die modules for over 5 years at least, before any determinations were made on what direction high NA EUV would go, and before it was even certain that any type of EUV would be the future. There are reasons to develop multi-die modules beyond a decrease in maximum die size using high NA EUV, such as flexibility in function through modularity (more economically targeting different markets with similar IP), flexibility in using different manufacturing processes for different parts of the chip (saving on cost for less critical functions, and I believe mixing analog and digital circuitry), more power efficient pooling of compute resources for parallel processors than allowed by inter-package communication such as CLX or NVLink, and allowing scalability of architectures from something targeting an edge device to something targeting a data center through the use of chiplets.
  • HollyDOL - Thursday, August 1, 2019 - link

    No worry, average marketing guy will find a way to market "subatomic" dimensions floor tiles :-)
  • extide - Wednesday, July 31, 2019 - link

    Yes Intel's first EUV will be their "7nm" process.
  • Santoval - Wednesday, July 31, 2019 - link

    "Does it start with its 7nm?"
    It does, however Intel have not yet disclosed how many (and which) layers they will fab with EUV, which is just as crucial. My guess is they will employ EUV for non crucial layers. Intel's delay of EUV is not surprising. The cause is, again, their super long delay of their 10nm node. Its design was fixed many, many years ago and it predicted no EUV use (they used quad patterning instead, specifically self aligned quad patterning, for the finest details).

    Intel have been fixing, debugging, optimizing, re-fixing etc their extremely complex (even for today's standards) 10nm node ever since its design was "fixed". Much more than its high transistor density (which is high in only one of its 3 variants) the reasons for the super long delay are the multiple new technologies Intel introduced at the same time, which greatly increased complexity and costs, and reduced yields. This was a strategic mistake on the part of Intel and the true reason of Brian Krzanich's departure.
  • Yojimbo - Thursday, August 1, 2019 - link

    They will use EUV for critical layers and non EUV for everything else. Why would they use it where they don't have to? The question is how many more layers of EUV they will add beyond what is absolutely necessary, and that will depend on the productivity of the EUV tools they can achieve as well as the cost and defects they are seeing when pushing the DUV tools to do it by using multi-patterning.
  • Santoval - Friday, October 11, 2019 - link

    "Do we know Intel's EUV plan? Does it start with its 7nm?"
    Yes it does. They have already said they are going to use EUV lithography at 7nm but not for how many layers. Intel target at least 200 million transistors per mm^2 for their 7nm node (the 200+ MTr/mm^2 number was reported by Intel; according to SemiWiki TSMC target ~185 MTr/mm^2 at 5nm and Samsung target a mere ~125 MTr/mm^2 at 5nm, which is just ~20% denser than Intel's 10nm node).

    At a transistor density of 200+ MTr/mm^2 even SAQD is insufficient, so Intel need EUV. Beyond the transistor (FEOL) stack Intel's biggest problem is with the lowest two layers (M0 & M1) of their BEOL stack. At 10nm they replaced the two lowest layers (which have the thinnest wires) with cobalt, because copper could no longer cut it due to skyrocketing resistance (which increases as the wires get thinner) and some other reasons.

    These cobalt nanowires were one of the most severe issues (they contributed to the very long launch delay, the lower clocks and the lower power efficiency Intel's 10nm has than it should have had) Intel faced at 10nm, and at 7nm they would need to get *much* thinner still, which might be out of the question. Intel can still etch them with EUV with not much difficulty, but that is not the problem. The problem is that Intel will probably need to switch to another material again, with uncertain consequences.
  • Santoval - Friday, October 11, 2019 - link

    correction : "At a transistor density of 200+ MTr/mm^2 even *SAQP* is insufficient.."
  • trivik12 - Wednesday, July 31, 2019 - link

    Samsung has not yet released single 7nm product and they have announced 3 more. More marketing bullshit. Let us see how note 7 9825(hopefully on 7nm) does before judging their plans.
  • CiccioB - Wednesday, July 31, 2019 - link

    But Nvidia that has announced Samsung as a foundry for its (probably just partially) next GPUs, which PP is going to use?
    I can't see a PP made for something that is not LP, and GPUs are complex and energy hungry AFAIK.
  • sseemaku - Wednesday, July 31, 2019 - link

    They might as well call it 10 pico meter considering its a marketing name anyway without the traditional 50% scaling!
  • JSS - Sunday, September 29, 2019 - link

    What do you mean "it's a marketing name"? Are the transistors in the 7LPP not 7nm in size? And 6nm in size in the 6LPP, and 5nm in size in the 5LPE, and 4nm in size in the 4LPE?
  • melgross - Wednesday, July 31, 2019 - link

    A lot of how this goes is now dependent on the trade war Japan is having with S Korea. Samsung is expected to have production problems because certain products, chemicals, etc. are either not being shipped, or delayed, or shipped in smaller quantities to Korean companies, particularly Samsung.

    No one knows where this is going. Japan is claiming to be insulted by S Korea allowing lawsuits and claims against the Japanese for a number of things that happened before and during WWII. And we know that the Japanese admit to nothing in that regard. It’s why there are still diplomatic problems with China, and other countries in that area.
  • Gc - Wednesday, July 31, 2019 - link

    I've read that South Korea and Japan negotiated a treaty in 1965 that finalized compensation, but the South Korean government kept some of the terms secret from its people until 2005, and the leaders used the funds for development rather than compensating individuals.
    https://en.wikipedia.org/wiki/Treaty_on_Basic_Rela...
  • melgross - Wednesday, July 31, 2019 - link

    I’m not so sure about how accurate that was.
  • s.yu - Thursday, August 1, 2019 - link

    I read about largely the same story in Chinese.
    One of the clauses in the treaty was supposedly that SK forgoes any rights to make further claims, both by the government and by individuals. In the past Japan has largely yielded to similar extortions from SK, but this time Japan judged that retaliating will lead to very little consequence, while it would deter similar actions in the future.
    I also read that Moon's motive in allowing the matter to develop is as a leftist he wants to use Japans countermeasures to weaken the megacorporations in order to rein them in.
  • anonym - Saturday, August 3, 2019 - link

    I think it won't affect, because still SK stands advantageous position than Taiwan and China.
    Maybe SK government need more approval rate.
  • 0iron - Thursday, August 1, 2019 - link

    Why there's no 7LPE?
  • ekrandegisimi - Thursday, August 1, 2019 - link

    I've read that South Korea and Japan negotiated a treaty in 1965 that finalized compensation, but the South Korean government kept some of the terms secret from its people until 2005, and the leaders used the funds for development rather than compensating individuals.

    https://www.acilekrandegisimi.com/orjinal-ekranlar...
  • mitsuhashi - Thursday, August 1, 2019 - link

    That's Japan's version of the story. Korea's version is that the agreement did not cover individual conscripted laborers suing the individual Japanese companies that they had to work for. And that is what happened -- Korea's Supreme Court ruled in favor of the laborers, the Japanese companies refused to pay the $100k per person, Korea threatened to seize their assets. Japan demanded for Korea to undo the ruling, the Korean government told them that they can't due to separation of powers, Japan called Korea liars and started a trade war. Korea said WTF, Japan said it was because Korea was giving Japanese materials to North Korea to create bombs and chemical weapons, Korea called it stupid and threatened to go to WTO, Japan said they didn't mention anything about North Korea.

    There are other reasons for this trade attack. Abe wants to scrap the pacifist clause in Japan's constitution so that they can use their self defense forces like any other country's military. Every time he riles up anti-Korean sentiment, his and his ultra right wing party's ratings go up, and there was a major election in July. His buddies needed 70% of the seats to amend the constitution immediately, but they got 65% instead so the pursuit continues. FYI, Abe's grandfather was also a PM and he pursued the same constitution amendment in the 60s, only 20 years after getting nuked by the US and agreeing to the pacifist clause.

    There is no economic benefit to the trade war, as Japan is now a materials, parts, and equipment powerhouse while Korea is a finished goods powerhouse and the two buy and sell from each other heavily. Japan has a trade surplus as well as a tourism surplus with Korea, meaning anti-Japanese sentiment is going to erode that surplus. Yet Japan continues to pursue the trade war as Koreans go all out boycotting everything related to Japan.
  • s.yu - Thursday, August 1, 2019 - link

    "Korea's Supreme Court ruled in favor of the laborers...the Korean government told them that they can't due to separation of powers"
    What BS is that? Moon fired the last judge that ruled against this and installed one loyal to him, the whole Korean story is BS.
    Also SK lost at WTO.
  • MandiEd - Monday, August 12, 2019 - link

    South Korea won at WTO
    https://www.reuters.com/article/us-japan-southkore...
  • melgross - Thursday, August 1, 2019 - link

    What are you, a clone?
  • s.yu - Thursday, August 1, 2019 - link

    That's obviously a bot that replaced the proper link with a spam link.
  • AshlayW - Thursday, August 1, 2019 - link

    Um, guys/gals, so the "nanometre" number here is just BS at this point right? What measurement is it actually taken from?
  • JSS - Sunday, September 29, 2019 - link

    How is it bullshit? Are the transistors in the 7LPP not 7nm in size? And 6nm in size in the 6LPP, and 5nm in size in the 5LPE, and 4nm in size in the 4LPE?
  • JSS - Sunday, September 29, 2019 - link

    What the hell do you geniuses mean that the naming convention is just marketing? Are the transistors in the 7LPP not 7nm in size? And 6nm in size in the 6LPP, and 5nm in size in the 5LPE, and 4nm in size in the 4LPE?
  • Adonisds - Sunday, October 6, 2019 - link

    That's exactly what we mean, the transistors in 7LPP are not 7nm in size. There is nothing in the 7LPP that measures 7nm. A fab's 7nm process might have larger transistors than the 10nm process of another.
  • Adonisds - Sunday, October 6, 2019 - link

    You seem to find this hard to believe. Just go to wikichip or someplace else. There is plenty of data that confirms my previous comment

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