Microchip Announces PCIe 5.0 And CXL Retimersby Billy Tallis on November 11, 2020 4:15 PM EST
Microchip is entering the market for PCIe retimer chips with a pair of new retimers supporting PCIe 5.0's 32GT/s link speed. The new XpressConnect RTM-C 8xG5 and 16xG5 chips extend the reach of PCIe signals while adding less than 10ns of latency.
As PCIe speeds have increased, the practical range of PCIe signals across a circuit board has decreased, requiring servers to start including PCIe signal repeaters. For PCIe gen3, mostly-analog redriver chips were often sufficient to amplify signals. With PCIe gen4 and especially gen5, the repeaters have to be retimers that operate in the digital domain, recovering the clock and data from the input signal with awareness of the PCIe protocol to re-transmit a clean copy of the original signal. Without retimers, PCIe gen5 signals only have a range of a few inches unless expensive low-loss PCB materials are used, so large rackmount servers with PCIe risers at the back and drive bays in the front are likely to need retimers in several places.
Microchip's new XpressConnect retimers add less than 10ns of latency, considerably better than the PCIe requirements of around 50–60ns. This also helps make the new XpressConnect retimers suitable for use with CXL 1.1 and 2.0, which use the same physical layer signaling as PCIe gen5 but target more latency-sensitive use cases. These retimers are the first Microchip products to support PCIe 5.0, but the rest of their PCIe product lineup including PCIe switches and NVMe SSD controllers will also be migrating to PCIe gen5.
The XpressConnect retimers come in 8-lane and 16-lane variants, both supporting bifurcation to smaller link widths, so that a single retimer can be used for multiple x1, x2 or x4 links. The retimers conform to Intel's specification for the BGA footprint and pinouts of PCIe retimers (13.4x8.5mm for 8 lanes, 22.8x8.9mm for 16 lanes), so these chips will eventually be competing against alternatives that could be used as drop-in replacements.
Common uses for PCIe retimers will be on drive bay backplanes, riser cards, and on large motherboards to extend PCIe 5.0 to the slots furthest from the CPU. Retimer chips will not necessarily be needed for every PCIe or CXL link in a server, but they are going to be an increasingly vital component of the PCIe ecosystem going forward. PCIe/CXL connections with a short distance from the CPU to the peripheral and few connectors will usually not need retimers, and riser or adapter cards that use PCIe switches to fan out PCIe connectivity to a larger number of lanes will already be re-transmitting signals and thus don't need extra retimers.
Microchip's XpressConnect PCIe 5.0 / CXL 2.0 retimers are currently sampling to customers, and are being incorporated into an Intel reference design for PCIe riser boards. Mass production will begin in 2021.
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mdriftmeyer - Wednesday, November 11, 2020 - linkAny way to reduce legacy on Audio Interfaces/Video Interfaces for rack mount studio equpiment would be welcomed.
mode_13h - Wednesday, November 11, 2020 - linkSorry, but what does that have to do with anything?
And I assume you meant to say "reduce latency"? That depends a lot on where the latency is coming from.
Brane2 - Wednesday, November 11, 2020 - link10ns is far from insignificant on PCIe5. This is 40 bits worth of delay. With one retimer on every couple of inches, this is becoming the futile excercise.
It looks like whole point of PCIe is for industry to push retimers by the shovel.
tygrus - Wednesday, November 11, 2020 - linkMaybe they will use more PCIe 5.0 to 2 or more PCIe 4.0 to make use of the bandwidth & extend distance to extra devices. PCIe 5.0 for closest slot & then PCIe 4.0/3.0 for the rest.
The 10ns latency looks sufficient to capture a whole packet with checksum/ECC & then retransmit with accurate clock & cleaner signals. Analog amps would just multiply the blur.
Jorgp2 - Thursday, November 12, 2020 - linkWat?
azfacea - Wednesday, November 11, 2020 - linkcables and not PCB is needed inside servers. preferably optics, w/ transmitters built into the silicon.
Billy Tallis - Wednesday, November 11, 2020 - linkYes, cables help a lot—even copper rather than optical. A server designed to provide a few dozen front drive bays running at gen5 speeds really should put OCuLink or similar connectors as close to the CPU as possible, and spread out on the backplane so that each drive (or switch) is within a few inches of its cable. But motherboard layout doesn't always allow for optimal positioning of PCIe connectors, what with power delivery and DRAM slots taking up so much prime real estate.
It'll be interesting to see what kind of system layouts are used in PCIe gen5 OCP servers, where all the storage and NICs are in front EDSFF slots, and no traditional PCIe add-in card slots in the rear.