Despite most discussion about chip manufacturing focusing on the leading edge and blazingly fast and complex side of the industry, the demand for the ‘legacy’ process technologies is also higher than ever, but also by volume a lot bigger than the latest and greatest. These legacy processes form the backbone of most modern electronics, and so being able to offer equivalent technology at lower cost/power is often a win-win for manufacturers and chip designers alike. To that end, Samsung is announcing a new 17nm process node, designed for customers still using a planar 28nm process, but want to take advantage of 14nm FinFET technology.

In modern processor design, a manufacturing process node comes with a set of design rules. To design a chip on that node, it has to follow those design rules. Usually those rules will have absolute worst-case limits, but if the chip designer can take advantage of the constraints to optimize their product, then it is of benefit to be intimately familiar with what can or cannot be done. As a result, a process like Samsung’s 28nm which uses planar transistors, will have a set of design rules different to that of Samsung’s 14nm, which uses 3D FinFET transistors. The design rules also take into consideration where to put the power, the connectivity, all the way up the metal stack from transistors to contact pads for packaging.

When it comes to manufacturing, at a high level there are two or three main segments to consider. The Front-End-Of-Line (FEOL) is where the manufacturing of the circuits starts, designing transistors. When we speak about leading edge technologies, it is the FEOL section that is inherently applied, because we need better and better tools to make smaller and smaller details in silicon to get the best transistors. Once the FEOL has done a number of layers with the transistors, the wafer moves to the Back-End-Of-Line (BEOL) for the rest of the circuitry – the BEOL takes care of putting in layers of connecting wires, power, and all the ancillary connections. After BEOL, the chips go to test, cutting up (dicing), and then packaging.

Sometimes the term Middle-of-Line or Middle-End-of-Line (MEOL) is used for chips with through-silicon-vias (TSVs) designed for multi-chip stacking.

At a holistic level, the FEOL and BEOL of any process node, say 28nm, has a 28nm version of design rules for both of those segments. Sometimes manufacturers will combine one set of design rules on FEOL with another on BEOL to produce a new product line, with some of the features of both. This is what Samsung is doing with its new 17nm / 17LPV (Low Power Value) process, announced today as part of Samsung's Foundry Forum event.

17LPV will combine the 14nm FEOL, so effectively the 14nm FinFET transistors, with a 28nm BEOL for connectivity. This means that customers can get the performance/power advantages of FinFET designs at an additional cost, without the extra cost of a denser BEOL. Ultimately the die size is likely still determined by the larger node BEOL, but the lower power transistors appear to be in demand. Samsung is claiming that 17LPV will over a 43% decrease in die area, 39% higher performance, or a 49% increase in power efficiency over a traditional 28nm process.

The first application for 17LPV will be in camera image signal processors, as part of Samsung’s CMOS Image Sensor portfolio. These chips aren’t necessarily requiring density, which makes 17LPV a good fit, but the optimized power and cost will benefit a specialised technology involved in stacking. Beyond that, Samsung is integrating 17LPV into its High Voltage offerings, targeting DDIC/Display Drivers that require high voltage support on the back-end combined with logic improvements.

Beyond 17LPV, Samsung Foundry is creating a 14LPU (we think this is still 28nm BEOL + 14nm FEOL) or Low Power Ultimate, for use with embedded MRAM and microcontrollers. 

The exact time scales of this new node have not been disclosed at this time, although Samsung Foundry’s representatives called the node part of a ‘paradigm shift’ inside the company when it comes to developing new specialty process solutions for these markets.

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  • Wereweeb - Wednesday, October 6, 2021 - link

    Didn't Ian say that the 28nm node still had the lowest cost per transistor? I wonder if this node aims at being cheaper than 28nm in every way except initial costs.

    Could they reduce the processing steps/masks required by relaxing the design rules, while keeping it IP compatible? Or is most of the added complexity/costs relative to 28nm inherent to finFETs?
    Reply
  • Kangal - Thursday, October 7, 2021 - link

    That was from a lecture by someone else. Can't remember who or where, but it was from someone knowledgeable in the field (Computer Scientist?). But it is true.

    However, whilst the 24nm-class of silicon used to have the lowest cost/transistor, and it will continue to do so. I remember seeing the projections for 16nm coming close to it. Which obviously isn't the case today due to the inflated market. But when things blow over in 2022/2023, that is how it will settle.

    I say this because, that extra cost to leap to 16nm-class, is actually worth it from a battery life or performance point of view for many products. And that's why SMIC had been on the fast-track to hit those targets by 2020-2022. It's just financially lucrative. SMIC and others also have plans to develop a 8nm-grade silicon sometime in the near future, which would help ease tensions between China (and it's military) for access and capabilities, against the products controlled by Taiwan and USA.
    Reply
  • Wereweeb - Thursday, October 7, 2021 - link

    I am aware 16nm/14nm is closing it in price. But if Samsung is creating an intermediary node distinct from their 14nm, it must be either because

    1) They can price match/make it cheaper than 28nm for the consumers that can afford re-designing their chips and would benefit from a node shrink, or
    2) Because they can reuse older equipment to fab more modern silicon (and it's unlikely they have old equipment laying around in a silicon shortage.)
    Reply
  • Kangal - Friday, October 8, 2021 - link

    I think it's a bit of both. And a third option; to show they are continuously innovating on all sectors.

    It makes no sense, to a big company which only requires a moderate node like 28nm, (eg Flash Module) to go to the effort of re-designing their product for this weird 18nm hybrid step, only to gain a slight improvement in cost and efficiency and performance. If you're at that point, you would have bitten the bullet and re-designed using the full 16nm node, paid a slight premium, and know that your product will be competitive for some long time.

    So I'm not too impressed with this showing. Had they introduced this back in 2015-ish then it may have been useful and gained traction, as these companies/products were transitioning from the 48nm-class of transistors. But by 2018, most of them had already transitioned their low-margin/high-volume products on to TSMC's 28nm, Samsung's 32nm, and GlobalF's 28nm transistors.
    Reply
  • Wereweeb - Monday, October 11, 2021 - link

    It's probably just a 14nm with relaxed specs, so they should be design-compatible. And there are applications where cost overrides any other concerns (MCU's, for instance).

    For a consumer it makes sense to just get the slightly better thing and not worry about it, but for volume-based electronics companies, every cent matters.
    Reply
  • Roland00Address - Thursday, October 14, 2021 - link

    Sophie Mary Wilson is the likely source. She was one of the main designers for ARM in 1983, and now works for Broadcom.

    Ian did a video on this at Youtube on his TechTalkPotato account "The True Cost of Processor Manufacturing: TSMC 7nm" some months ago. And he cited Sophie Wilson. Note it is not just the cost per transistor, but the cost per transistor that is **useable** and turned on at a specific time measured in fractions of a second. For 90nm you can have about 5/6ths of the gates active at the same time, but for 7nm you can only use about 6/10ths of the gates active at the same time due to power and heat reasons, you have to have some of the silicon "temporary" turned off and this is called dark silicon. Thus higher cost per wafer at smaller density for features (but you also get more features per chip), and power reason makes 28nm at this moment the cheapest cost per transistor as of 2016. Of course that is 5 years ago so the price per wafer may be out of date even though lots of the technical stuff with density and other characteristics will not have changed.
    Reply
  • eastcoast_pete - Wednesday, October 6, 2021 - link

    They will have some customers for sure, but the need to redesign almost from scratch really hurts in a segment that is usually very cost-sensitive. But, right now, people are desperate for ICs, so they'll get their customers.
    What I'd like to know if going to 17 nm FinFet will increase the number of chips Samsung can get per wafer?
    Reply
  • MrCommunistGen - Wednesday, October 6, 2021 - link

    It does state that there's an expected decrease in die area over traditional 28nm. Reply
  • Oxford Guy - Thursday, October 7, 2021 - link

    But how does it compare to 14nm?

    Who cares if it's better than 28nm if there is a better value to be found in a more recent process? Now, I understand that it's a given that we're to assume that this is supposed to be a better value than 16/14/12nm alternatives. However, to only provide a comparison with 28nm is inadequate.

    How much more die area? How much lower performance? How much worse power efficiency? How much better performance-per-dollar?
    Reply
  • MrCommunistGen - Wednesday, October 6, 2021 - link

    Oof. Meant to put this in my first reply:

    I imagine the intent is for 17LPV to be for new designs, not die shrinks of existing designs.
    Reply

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